Immediate operands won't accept a duplication factor...why not ?
Can't find a reason in the HLASM manual
Try these...
CFI R1,4X'FF'
CFI R1,X''
CFI R1,-1
AHI R1,2X'FF'
AHI R1,X''
AHI R1,-1
Melvyn Maltz
To restate what I'm asking for...
Now that we have 2 and 4-byte immediate values it would make sense
to allow both duplication factor and explicit length for these
Currently the instructions below would fail
AHI 1,2X'FF'
CFI 1,XL4'FF'
Rather more contentious, I agree, is to
10, well we still do B *+10
It's 10 halfwords
I've also noticed that the HLASM output listing is very inconsistent about
immediate operands, when I've done further research I'll include it in my RFE
Melvyn Maltz.
- Original Message -
From: "Tom
Hi Paul,
A pity our Emails crossed, with regards to the 2X'FF issue please read my
latest post
As for the Scon...I agree with you, you must submit a bug report for that
one
Regards,
Melvyn.
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.e
and W messages assemble
correctly, except the last LHI which has the invalid 2AL1...doh
Melvyn Maltz.
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Saturday, March 18, 2017 2:10 PM
Subject: Re: HLASM "Ano
be drawn to the Programmer's intent, did they mean
to code LGFI ?
Melvyn.
- Original Message -
From: "Paul Gilmartin" <0014e0e4a59b-dmarc-requ...@listserv.uga.edu>
To:
Sent: Saturday, March 18, 2017 10:21 PM
Subject: Re: HLASM "Anomaly"
On 2017-03-18,
UK and then be submitted to IBM. It will be up to IBM to judge
the cost/benefit factors
Let me restate, whatever form the final RFE takes it will not affect current
code, though it may produce warning messages not previous produced, eg. for
LHI 1,X'' which has aleady been di
better than it does at present
Melvyn Maltz.
- Original Message -
From: "Peter Relson"
To:
Sent: Saturday, March 25, 2017 8:30 PM
Subject: Re: HLASM "Anomaly"
Regarding the lengthy discussion of immediate operands and whether there
should be warnings or errors,
S and did sufficent damage to cause the CICS region to
crash
I raised an APAR
Melvyn Maltz.
- Original Message -
From: "Steve Thompson"
To:
Sent: Friday, May 12, 2017 3:07 AM
Subject: Re: Quick error termination of an assembler routine (Was: Performance
of Decimal Floating Poin
time until you have none
left
Regards,
Melvyn Maltz.
- Original Message -
From: "Richard Kuebbing"
To:
Sent: Tuesday, May 16, 2017 9:28 PM
Subject: random quest
So I need a set of 99,999 random numbers which are 5 digits and unique, i.e.
no duplicates. CEERAN0 and Cobol
Hi Richard,
Paul is right, we came up with the same solution
There are several statistical tests for randomness, perhaps the easiest to
calculate is MSSD (mean squared successive differences) and you are on the
right track
You can attach my name
Melvyn.
- Original Message -
From:
rs of assembler coding and still no-one listens to me.
And just to annoy people even more, enhancing the IBM360 architecture is
like redesigning the T-Rex...it's already extinct guys...time to move on.
Melvyn Maltz.
- Original Message -
From: "Gary Weinhold"
To:
Sent: Su
pe expression for 2 or
4-byte immediates unless the feeling is strong enough
One last point, as I don't work for an IBM customer I have no access
to the formal method of submitting an RFE. If the general feeling here
is that one should be submitted may I ask for someone to do this on my
behalf
Melvyn Maltz.
n't and I would appreciate you guys finding it
and responding
Melvyn Maltz.
- Original Message -
From: "Charles Mills"
To:
Sent: Monday, December 11, 2017 10:16 PM
Subject: Re: Macro Processors
I get your point. The assembler macro facility is more like a facility for
writi
From: "Charles Mills"
To:
Sent: Monday, December 11, 2017 11:50 PM
Subject: Re: Macro Processors
Who is us guys and if it bounced, how would we respond?
Charles
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf O
mbler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of MELVYN MALTZ
Sent: Monday, December 11, 2017 4:00 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Macro Processors
Sorry Charles, I wasn't precise
The post is there, but the return of my post went into my Spam folder, which
it has
For some reason my recent posting is going into Spam or (in my case) being
rejected as Spam before I get it
It isn't Spam and is a topic for further discussion
The Posting is called: HLASM RFE revisited
Posted on: 11th Dec @ 09:36
It can be found on the listserv website
Perhaps the moderator w
u...@listserv.uga.edu>
To:
Sent: Thursday, December 14, 2017 5:23 PM
Subject: Re: Posting
On Wed, 13 Dec 2017 17:26:51 -0500, Melvyn Maltz wrote:
For some reason my recent posting is going into Spam or
(in my case) being rejected as Spam before I get it
If I understand correctly, you are sayin
day, December 14, 2017 8:05 PM
Subject: Re: Posting
On 12/14/2017 12:03 PM, MELVYN MALTZ wrote:
Did you receive the original post ? If not...why ?
Irrelevant. Every spam filter is unique. Your experience with your
particular spam filter is unique to you on no one else...
--
Phoenix Software
the planet ?
Melvyn Maltz
- Original Message -
From: "Farley, Peter x23353"
To:
Sent: Wednesday, March 14, 2018 10:18 PM
Subject: Re: Two string instruction questions
I think I read somewhere that is what keyed VSAM Index records are, aren't
they? A count of equ
Hi Paul,
Others will give you code
Define an LCLC array
Keep a count of entries
Before inserting a new entry, scan the array to see if &XCODE is already
there
If it is...it's a duplicate
If not, add it and increment the count
Melvyn Maltz
- Original Message -
Fr
block
Register notation is invalid with MF=L
Melvyn Maltz.
- Original Message -
From: "Tony Harminc"
To:
Sent: Tuesday, July 02, 2019 8:54 PM
Subject: Re: C DLL Code from Assembler
On Tue, 2 Jul 2019 at 12:50, John McKown
wrote:
Wouldn't it be nice if IBM wer
are made available before the next major hardware level this
will not result in any new potential clashes with library macros.
Melvyn Maltz.
- Original Message -
From: "Charles Mills"
To:
Sent: Sunday, December 01, 2019 9:03 PM
Subject: Re: Where do I find more info abo
As part of a training exercise I was challenged to write code that abended S0C5
While I'm very skilled at writing Assembler code that abends, I failed in this
case :-(
With the advent of much more secure storage allocation (if someone mentions
CICS Storage Violations the men in white coats will
Interrupt Code (PIC) 5.
I can't remember off the top of my head if this is addressing or
specification exception.
Regards,
Steve Thompson
On 1/29/20 4:11 PM, Melvyn Maltz wrote:
As part of a training exercise I was challenged to write code that
abended S0C5
While I'm very skilled at wr
at 3:23 PM, Steve Thompson wrote:
Get the PoOP and look at Program Interrupt Code (PIC) 5.
I can't remember off the top of my head if this is addressing or
specification exception.
Regards,
Steve Thompson
On 1/29/20 4:11 PM, Melvyn Maltz wrote:
As part of a training exercise I wa
s, you can use it to generate system anend
codes.
PIC 5 is basically that a physical address doesn't exist, so I doubt you
can generate it DAT on.
On Wed, Jan 29, 2020, 15:11 Melvyn Maltz <
072265160664-dmarc-requ...@listserv.uga.edu> wrote:
As part of a training exercise I was cha
Hi Keven,
You might be the 5th, but the response is respected
I didn't know the LURA and STURA instructions but these require privops
access
From other responses I conclude that S0C5 is not possible with DAT on, but I
still feel that it's more to do with storage key protection than DAT
Agai
Hi Steve,
You're the only person to actually meet my request...thankyou
I would much appreciate the code used, I tried B and MVI to your address in
A/RMODE 31 but I get S0C4
Melvyn.
- Original Message -
From: "Steve Smith"
To:
Sent: Thursday, January 30, 2020 12:39 AM
Subject: Re:
problem
I don't know Linux, but I know someone who does
Melvyn Maltz.
- Original Message -
From: "Frank Myers"
To:
Sent: Monday, May 11, 2020 11:05 PM
Subject: Z390 Assembler Emulator
Hi,
I installed the z390 emulator and assembler on Linux. I tried to assemble
some
Hi JD,
Download the z390 product (it's free) from www.z390.org
It's an Assembler emulator for a PC under Windows or Linux
I teach and mentor students of Assembler and would be happy to help you in
any way
z390 has it's own forums as well
Contact me here zarf77...@blueyonder.co.uk
Regards,
Me
t IBM do this in the VSAM TESTCB macro
Melvyn Maltz.
- Original Message -
From: "David Woolbright"
To:
Sent: Tuesday, June 02, 2020 5:58 PM
Subject: Re: z/OS HLASM: EQU for statement labels
I’’m just a humble academic so I hesitate to weigh in. I trained assembler
program
a sign,
If you find a plus just set it to X'F0'
If you find a minus, set it to X'F0' and use NI to set the last byte to
X'nD'
Then use CDZT or CXZT to convert to DFP
Using DFP is better than the old packed instructions
I expect there will be dissenters
Melvyn
Assembler development work for zVSAM V2
Melvyn Maltz.
- Original Message -
From: "Dan Greiner"
To:
Sent: Tuesday, July 14, 2020 6:51 PM
Subject: z390 Macros for Newer Instructions
I continue to noodle around with z390 and regularly find myself missing
support for newer instruct
ere a central location that contains the current z390? The
z390.org web site looks like it hasn't been updated in quite some time.
Can we discuss this off-list?
Regards, John Ganci
On Tue, 2020-07-14 at 20:07 +0100, MELVYN MALTZ wrote:
Hi Dan,
I know Don Higgins is working on bringing z390
uction for an EX
Would this have the same performance hit ?
Melvyn Maltz.
ould be refreshed,
a minor overhead provided is wasn't being done a lot
I'm still a little concerned that TESTCB might be used internally by COBOL
etc and be taking a performance hit unknown to the users
Melvyn Maltz.
- Original Message -
From: "Christopher Y. Blaiche
o on
And using an index register instead of a base register is frowned upon
(440D0014)
I doubt if it matters now, but you are right, back in 360/370 days the use
of index carried a 50uS overhead
I well remember obsessively recoding LA R5,1(R5) as LA R5,1(,R5) back in the
days
Me
Apologies, I misremembered
Found a Functional Characteristics for the 360/50 and it's 0.5uS
Melvyn Maltz.
- Original Message -
From: "Seymour J Metz"
To:
Sent: Wednesday, October 28, 2020 6:51 PM
Subject: Re: Is TESTCB a bad boy ?
WTF? Yes, on some models index was
I have to thank my esteemed colleague Don Higgins for enabling this post
IILF R3,MYLABEL
...
MYLABEL DC 'HELLO'
This is interesting on a number of levels, yes, the immediate value is
relocatable
I guess this is a 'good thing' for 32-bit immediate instructions...hmmm
My concern is though, are th
error code
Whether this is worth doing is largely up to the user community, I would be
worried if an innocent looking macro could subvert program code
Your thoughts ?
Melvyn Maltz.
the full program, I tested it and it works
R5 doesn't contain a DCB address.
I know...OPEN wouldn't get that far because the end-of-list bit stays with
DCB 1
I'm using R5 to do something nasty to storage beyond the MF=L
Melvyn Maltz.
- Original Message -
From: "Se
the LARL happy
LARL has a range of +/- 2G which should keep most coders happy, so it
doesn't matter where the LTORG is
Melvyn Maltz.
On 08/11/2021 12:25 am, Tony Thigpen wrote:
I finally am to the point where I no longer need to worry about
specific customers having hardware that does not
Hi there,
I am sure Jonathan will confirm...but yes, even byte literals will be on
an even boundary, they are sorted
If you code it and use LARL, you'll get an error if not on an even boundary
=CL5 may not align, a frequent source of 'it worked then but not now'
syndrome
Me
Hi Ray,
No need for a z15, z390 supports them :-)
Melvyn.
On 14/12/2021 01:06 pm, Ray Mansell wrote:
Excellent stuff, as always, Dan. Now, if only I could find a z15 on
which to play :-)
Ray
On 12/14/2021 12:03 AM, Dan Greiner wrote:
Back in late September, I posted a series of PowerPoint s
#x27; per instruction,
hyperlinks to similar instructions, maybe a tracker saying 'people who
looked at AHI also looked at LHI :-)'
Perhaps there's someone out there who has the time
Melvyn Maltz.
On 10/02/2022 07:40 pm, David Cole wrote:
WRT:
"A gentle reminder on term
One can see why the Principles of Operation manual (PoP) was designed in its
present format...to save paper.
There is now no need to design this manual in a form that was suitable 30 years
ago.
Now that I've restarted teaching Assembler I realise that the PoP neither
serves the professional le
BLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Melvyn Maltz
Sent: Wednesday, November 12, 2014 4:04 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Redesigning the Principles of Operation Manual
One can see why the Principles of Operation manual (PoP) was designed in
its present format...to save paper.
You might also like to know of an undocumented instruction specific to the
360/20.
This was a form of the Diagnose (opcode X'83') which allowed me to read the hex
dials
on the console into storage.
This was extremely useful as I had the job of converting 1401 Autocoder into
360/20 Assembler
and
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