On 8/20/2010 9:16 AM, Steve Comstock wrote:
THEPROG CSECT
STM 14,12,12(13)
LR 12,15
USING THEPROG,12,11,10
BAS 2,*+8
DC F'4096'
L 2,0(2)
LA 11,0(2,12)
LA 10,0(2,11)
My program start macros use:
LR R12,R15
LA R10,2048
LA R11,2048(R10,R12)
LA R10,2
McKown, John wrote:
-Original Message-
From: IBM Mainframe Assembler List
[mailto:assembler-l...@listserv.uga.edu] On Behalf Of Steve Comstock
Sent: Friday, August 20, 2010 8:17 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
THEPROG
On Aug 20, 2010, at 07:51, McKown, John wrote:
>
> Good point on the pipeline. I am constantly forgetting about pipeline delays.
>
Is there a tool to analyze and report these? I recall
that decades ago there was such for CDC 6600.
-- gil
> -Original Message-
> From: IBM Mainframe Assembler List
> [mailto:assembler-l...@listserv.uga.edu] On Behalf Of David Bond
> Sent: Friday, August 20, 2010 8:45 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: CDS and alignment question
>
> On Fri, 20
On Fri, 20 Aug 2010 08:26:28 -0500, McKown, John wrote:
>THEPROG CSECT
> STM14,12,12(13)
> LR 12,15
> USING THEPROG,12,11,10
> LAY11,4096(,12)
> LAY10,4096(,11)
I realize that the STM implies that the program is not in 64-bit mode, but a
bet
> -Original Message-
> From: IBM Mainframe Assembler List
> [mailto:assembler-l...@listserv.uga.edu] On Behalf Of Steve Comstock
> Sent: Friday, August 20, 2010 8:17 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: CDS and alignment question
>
> --
Tony Thigpen wrote:
I always like to use a second register with a value of +1
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LRR11,R15
LAR14,1
USING QMGREX01,R11,R12
LAR12,4095(R14,R11)
LRR8,R1
USING WORKAREA,R13
It is even
I always like to use a second register with a value of +1
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LRR11,R15
LAR14,1
USING QMGREX01,R11,R12
LAR12,4095(R14,R11)
LRR8,R1
USING WORKAREA,R13
It is even move meaningful if usi
Paul Gilmartin wrote:
On Aug 18, 2010, at 20:33, Steve Smith wrote:
Furthermore, it is incorrect to put a USING statement before it is valid
(although it is fairly common). It should be moved after your commented
line. The USING for R13 is also obviously premature.
What do you do when you'
We concluded that having two forms of USING (or a new USING statement)
to accommodate both short and long displacements could be rather
confusing, especially when you have to consider negative displacements,
overlaps with normal 0-4095 ranges, etc. It didn't seem a very high-
priority need.
John Eh
Gil,
(or should I use Paul?)
>> Is there any form of USING for multiple base registers and long
displacements,
Multiple is (per documentation) 4096 and then the next.
>> or is it merely unthinkable that any DSECT would
require multiple base registers with long displacements? <<
that would be a
On Aug 19, 2010, at 09:12, David Bond wrote:
>
>>
> Given:
> USING DSA,R13,R12
> or:
> USING DSA,R13
> USING DSA+4096,R12
> with:
> USING (IHADCB,IHADCB+DCBLNGQS),SYSPRINT
> MVC DCBDDNAM,=CL8'SYSOUT'
> ...
> DSA DSECT
> ...
> SYSPRINT DCB ... (genera
On Thu, 19 Aug 2010 08:48:34 -0600, Paul Gilmartin wrote:
>> If for instance, a DCB crosses base registers and the DCB fields are to be
>> referenced via a based USING on the IHADCB DSECT, the difference between
>> the two matters. It works only if the single USING statement is employed.
>> I have
On Aug 19, 2010, at 07:25, David Bond wrote:
> Ensuring the base registers are 4096 apart is important when using based
> USINGs for items within the referenced area. A 4095 increment requires
> separate USINGs for each register, resulting in separate USING ranges. A
> 4096 increment allows a sing
and code properly.
Lloyd
- Original Message
From: Tom Marchant
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Thu, August 19, 2010 9:12:46 AM
Subject: Re: CDS and alignment question
On Thu, 19 Aug 2010 05:32:15 -0700, Lloyd Fuller wrote:
>And BOTH of the LA commands shown are bad cod
On Wed, 18 Aug 2010 23:27:30 -0600, Paul Gilmartin wrote:
>On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
>
>> I think the original posting was pointing out that you lose only
>> a single byte of addressability by adding 4095, and that you save
>> one instruction. The added
Ensuring the base registers are 4096 apart is important when using based
USINGs for items within the referenced area. A 4095 increment requires
separate USINGs for each register, resulting in separate USING ranges. A
4096 increment allows a single USING statement and a contiguous USING range.
If f
TSERV.UGA.EDU
>Sent: Thu, August 19, 2010 1:27:30 AM
>Subject: Re: CDS and alignment question
>
>On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
>
>
>
>>(-- Referenced Note Follows )
>> Sent: Wednesd
nning in AR mode.
Lloyd
- Original Message
From: Paul Gilmartin
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Thu, August 19, 2010 1:27:30 AM
Subject: Re: CDS and alignment question
On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
>(-- Refe
On Aug 18, 2010, at 20:33, Steve Smith wrote:
>
>
> Furthermore, it is incorrect to put a USING statement before it is valid
> (although it is fairly common). It should be moved after your commented
> line. The USING for R13 is also obviously premature.
>
What do you do when you're marching throu
On Aug 18, 2010, at 17:30, John R. Ehrman (408-463-3543 T/543-) wrote:
> I think the original posting was pointing out that you lose only
> a single byte of addressability by adding 4095, and that you save
> one instruction. The added byte is rarely an issue; whether or not
> the extra instruction
On Wed, 18 Aug 2010 22:33:27 -0400, Steve Smith wrote:
It is the typical way to do it. However, long ago, someone pointed out
that this sequence burns 4 bytes to add 1 byte of addressability.
And to preserve the sanity of any poor soul who has to look at the resultant
listings or a dump. Hec
It is the typical way to do it. However, long ago, someone pointed out
that this sequence burns 4 bytes to add 1 byte of addressability.
Which, to Mr Spock, makes no sense.
Furthermore, it is incorrect to put a USING statement before it is valid
(although it is fairly common). It should be move
I think the original posting was pointing out that you lose only
a single byte of addressability by adding 4095, and that you save
one instruction. The added byte is rarely an issue; whether or not
the extra instruction is important depends on the application.
John Ehrman
(-- Re
On Wed, 18 Aug 2010 16:16:58 -0500, McKown, John wrote:
>> -Original Message-
>>
>> I have always used something like this:
>>
>> QMGREX01 CSECT ,
>> STM R14,R12,12(R13)
>> LRR11,R15
>> USING QMGREX01,R11,R12
>> LAR12,4095(R11)
>> LA
ike S
Sent: Wednesday, August 18, 2010 3:51 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
I have always used something like this:
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LRR11,R15
USING QMGREX01,R11,R12
LAR12,4095(R11)
ike S
Sent: Wednesday, August 18, 2010 3:51 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
I have always used something like this:
QMGREX01 CSECT ,
STM R14,R12,12(R13)
LRR11,R15
USING QMGREX01,R11,R12
LAR12,4095(R11)
L
> -Original Message-
> From: IBM Mainframe Assembler List
> [mailto:assembler-l...@listserv.uga.edu] On Behalf Of Ward, Mike S
> Sent: Wednesday, August 18, 2010 3:51 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: CDS and alignment question
>
> I have al
ING WORKAREA,R13
Is this not the way to do it?
-Original Message-
From: IBM Mainframe Assembler List
[mailto:assembler-l...@listserv.uga.edu] On Behalf Of glen
herrmannsfeldt
Sent: Tuesday, August 17, 2010 1:56 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
On Tue, 17 Aug 2010 16:09:41 -0400, Alex Kodat wrote:
>AFAIK, cache block size has always been at least a multiple
>of 128 on 360 and upward machines.
I know that the cache line on the Amdahl 470 series was 32 bytes.
IIRC that was pretty typical, for those machines that had cache.
Not all did at
requiring more latches.
Bill Fairchild
Rocket Software
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu] On
Behalf Of Alex Kodat
Sent: Tuesday, August 17, 2010 3:10 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
On Tue, 17 Aug 2010 15:27:00 -0400, Chris Craddock wrote:
Why does the data for a CDS need to be on a doubleword anyway?
"It just does"
Or if you want the more gory explanation... it has to do with storage operand
consistency
rules...
More specifically, the CS, CDS, and CDSG instructions
> Why does the data for a CDS need to be on a doubleword anyway?
"It just does"
Or if you want the more gory explanation... it has to do with storage operand
consistency rules. CDS is built on top of the hardware memory architecture and
so it has to play within the same rules as other storage a
ECT ever does change.
-Original Message-
From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
On Behalf Of Mark Hammack
Sent: Tuesday, August 17, 2010 7:33 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
Yes, STGHEAD is in a DSECT:
ever does change.
>
> -Original Message-
> From: IBM Mainframe Assembler List [mailto:assembler-l...@listserv.uga.edu]
> On Behalf Of Mark Hammack
> Sent: Tuesday, August 17, 2010 7:33 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: CDS and alignment quest
It is the address in memory that matters.
This reminds me of programs with two base registers, using LA
to set the registers such that the offset of the second is 4095
from the first. All instruction addresses (an branch instructions)
will then have an odd offset, legal but it looks funny.
On th
-LIST@LISTSERV.UGA.EDU
Subject: Re: CDS and alignment question
Yes, STGHEAD is in a DSECT:
STGPOOL DSECT
STGSIZE DS F
STGHEAD DS A
STGCNTDS F
STGERRDSF
As I said in the original e-mail, the "easy" thing to do would be to
rearrange the dsect so th
On Aug 17, 2010, at 08:32, Mark Hammack wrote:
> Yes, STGHEAD is in a DSECT:
>
> STGPOOL DSECT
> STGSIZE DS F
>
> As I said in the original e-mail, the "easy" thing to do would be to
> rearrange the dsect so that STGHEAD is on a doubleword boundary (i.e. move
> STGERR before STGHEAD and
> From: IBM Mainframe Assembler List> [mailto:assembler-l...@listserv.uga.edu] On Behalf Of Mark Hammack> Sent: Monday, August 16, 2010 13:26> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU> Subject: Re: CDS and alignment question>> Thanks! However, I think you meant ACONTROL FLAG(NOALI
ainframe Assembler List
> [mailto:assembler-l...@listserv.uga.edu] On Behalf Of Mark Hammack
> Sent: Monday, August 16, 2010 13:26
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: CDS and alignment question
>
> Thanks! However, I think you meant ACONTROL FLAG(NOALIGN)/ACO
RV.UGA.EDU
Subject: Re: CDS and alignment question
Thanks! However, I think you meant ACONTROL FLAG(NOALIGN)/ACONTROL
FLAG(ALIGN). At least that is what worked for me.
Thanks again,
Mark Hammack
Senior Technical Specialist
Systemware, Inc.
On Mon, Aug 16, 2010 at 1:00 PM, Binyamin Dissen
wrote:
&g
Thanks! However, I think you meant ACONTROL FLAG(NOALIGN)/ACONTROL
FLAG(ALIGN). At least that is what worked for me.
Thanks again,
Mark Hammack
Senior Technical Specialist
Systemware, Inc.
On Mon, Aug 16, 2010 at 1:00 PM, Binyamin Dissen wrote:
> On Mon, 16 Aug 2010 09:45:39 -0500 Mark Hamma
On Mon, 16 Aug 2010 09:45:39 -0500 Mark Hammack
wrote:
:>I have a question about alignment that maybe someone will be able to
:>answer. I recently came across this in a piece of code:
:>BB68 5004 0004 31508 CDS R6,R8,4(R5)
:>According to the POO, " The second oper
I have a question about alignment that maybe someone will be able to
answer. I recently came across this in a piece of code:
BB68 5004 0004 31508 CDS R6,R8,4(R5)
According to the POO, " The second operand of COMPARE AND SWAP (CSG) and
COMPARE DOUBLE AND SWAP (CDS, C
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