John McKown asked:
| Why do I need to know the number of 1 bits in
| each individual byte in a GPR? Is it _that_
| common a question in application or system
| code?
Say you were an operating system software developer.
Let's further say that you wanted to write a really
efficient cell
|
| |
| View on blogger.popcnt.org | Preview by Yahoo |
| |
| |
From: Robin Vowels
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Wednesday, March 11, 2015 3:25 PM
Subject: Re: LZRG??? Does this mean that 56-bit addressing is "a thing"?
From: "John McKown"
Sent: Thu
I too would find that interesting.
Fred!
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of John McKown
Sent: woensdag 11 maart 2015 15:50
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: LZRG??? Does this mean that 56-bit
On Wed, Mar 11, 2015 at 9:58 AM, Mike Shaw wrote:
>
> On Wed, Mar 11, 2015 at 10:49 AM, John McKown
> wrote:
>
>> Given some of the new instructions, such as LGZR, I wish IBM would
>> publish a manual with a title like: "What were the architects thinking
>> of? Explanation of the reasons behind t
On Wed, Mar 11, 2015 at 10:49 AM, John McKown
wrote:
> Given some of the new instructions, such as LGZR, I wish IBM would
> publish a manual with a title like: "What were the architects thinking
> of? Explanation of the reasons behind the instructions in the z
> architecture".
> ...
>
"To ma
> Pages 7 to 8 of this presentation:
> https://share.confex.com/share/124/webprogram/Session16609.html
>
> Evidently the code with SIMD instructions is the equivalent of what the
> millicode does for SRST, but I may have misinterpreted what was said.
> Using the millicoded instruction is eviden
From: "John McKown"
Sent: Thursday, March 12, 2015 1:49 AM
Given some of the new instructions, such as LGZR, I wish IBM would
publish a manual with a title like: "What were the architects thinking
of? Explanation of the reasons behind the instructions in the z
architecture". Some are obvious,
On 11 March 2015 at 16:41, Paul Gilmartin <
0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
> On 2015-03-11, at 08:49, John McKown wrote:
> > And POPCNT is another
> > one. Why do I need to know the number of 1 bits in each individual
> > byte in a GPR?
> >
> Because CDC had it first? I
Pages 7 to 8 of this presentation:
https://share.confex.com/share/124/webprogram/Session16609.html
Evidently the code with SIMD instructions is the equivalent of what the
millicode does for SRST, but I may have misinterpreted what was said.
Using the millicoded instruction is evidently less ef
> When Dan Greiner used to present new hardware instructions at SHARE, he used
> to mention some had uses in micro/millicode. He talked about instructions he
> had personally pushed > for because he could see performance benefits by
> using them in millicode. Those of us attending couldn't thi
On 2015-03-11, at 08:49, John McKown wrote:
> And POPCNT is another
> one. Why do I need to know the number of 1 bits in each individual
> byte in a GPR?
>
Because CDC had it first? I suspect that it became a built-in
function in Pascal, CARD(), because Pascal was developed on a
CDC which had
Oops. I dyslex'd the whole thing. Nevermind.
At 3/11/2015 04:06 AM, Binyamin Dissen wrote:
Easy alignment to a 256 byte boundary?
When Dan Greiner used to present new hardware instructions at SHARE, he
used to mention some had uses in micro/millicode. He talked about
instructions he had personally pushed for because he could see
performance benefits by using them in millicode. Those of us attending
couldn't think of any
Given some of the new instructions, such as LGZR, I wish IBM would
publish a manual with a title like: "What were the architects thinking
of? Explanation of the reasons behind the instructions in the z
architecture". Some are obvious, like L, ST, A. But why a single
instruction to do this? Is it _t
Oops. I dyslex'd the whole thing. Nevermind.
At 3/11/2015 04:06 AM, Binyamin Dissen wrote:
Easy alignment to a 256 byte boundary?
On Tue, 10 Mar 2015 18:57:53 -0400 David Cole wrote:
:>Per the new PoOps:
:>
:>
:>>LZRG R1,D2(X2,B2) [RXY-a]
:>>
:>>The second operand, with the rightmost byt
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