> Conceptually,the MVCL instruction could treat cases that specified the
> same register pair for source and target operands as a request to clean or
> fill the designated storage area.
You'd have to change the current behavior of MVCL -- when the same register is
specified for both operands, it
bin Vowels [robi...@dodo.com.au]
Sent: Friday, April 15, 2022 5:08 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
- Original Message -
From: "Tom Harper"
To:
Sent: Friday, April 15, 2022 3:06 AM
IMHO, the next instruction to add to z/Architecture would
>
> -Original Message-
> From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
> On Behalf Of Tom Harper
> Sent: Friday, April 15, 2022 2:19 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: Next instruction needed
>
> Caution! This messag
pabilities.
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Tom Harper
Sent: Friday, April 15, 2022 2:19 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
Caution! This message was sent from outside your organi
frame Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On
Behalf Of Tom Harper
Sent: Friday, April 15, 2022 11:19 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
I think that is unnecessary because the proposal is only for one to 256 bytes
so no need to make it i
I think that is unnecessary because the proposal is only for one to 256 bytes
so no need to make it interruptible. If you want to use for longer areas, use a
move long.
Many instructions have been added over the years for small items. This would
find significant use as soon as the instruction
On Apr 15, 2022, at 11:34:40, Tom Harper wrote:
>
> If it was interrupted, where would the hardware restart? The instruction
> itself cannot be changed.
>
Make it an RFE. Support it with a business case, that it would provide added
value to end users inducing them to spend more on IBM equipme
Harper
> Sent: Friday, April 15, 2022 10:11 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: Next instruction needed
>
> [EXTERNAL EMAIL] DO NOT CLICK links or attachments unless you recognize
> the sender and know the content is safe.
>
> For a fixed length move,
If it was interrupted, where would the hardware restart? The instruction itself
cannot be changed.
Sent from my iPhone
> On Apr 15, 2022, at 1:19 PM, Dave Clark wrote:
>
> "IBM Mainframe Assembler List" wrote on
> 04/15/2022 01:10:36 PM:
>> For a fixed length move, none. For a variable len
Zero is nothing after all.
Charles
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU]
On Behalf Of Paul Gilmartin
Sent: Friday, April 15, 2022 9:49 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
On Apr 15, 2022
"IBM Mainframe Assembler List" wrote on
04/15/2022 01:10:36 PM:
> For a fixed length move, none. For a variable length move, one.
Why not zero registers required for a variable length initialize?
For an extended displacement instruction such as what follows, the second
full-word para
For a fixed length move, none. For a variable length move, one.
Sent from my iPhone
> On Apr 15, 2022, at 12:27 PM, Robin Vowels wrote:
>
> On 2022-04-16 02:23, Tom Harper wrote:
On Apr 15, 2022, at 12:20 PM, Robin Vowels wrote:
>>> On 2022-04-16 00:25, Tom Harper wrote:
Well know
Tom Harper made a perfectly clear proposal, that evidently only you cannot
comprehend.
I have my own opinion on its value, but I for one, don't think the world
needs to know every opinion I happen to have.
sas
>
>
On Apr 15, 2022, at 10:27:47, Robin Vowels wrote:
>
> On 2022-04-16 02:23, Tom Harper wrote:
>>>
>> As mentioned, R0.
>
> Make up your mind! You just said that no registers were involved.
>
R0 doesn't count because no one else uses it.
--
gil
On 2022-04-16 02:23, Tom Harper wrote:
On Apr 15, 2022, at 12:20 PM, Robin Vowels
wrote:
On 2022-04-16 00:25, Tom Harper wrote:
Well known. But the instruction I’m proposing has no registers
involved
Oh? How do you propose that such an instruction move
N bytes (where N is variable) with
illicode to periodically check
>>> for pending interrupts and update the registers as needed
>
>>>
>>> From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on
>>> behalf of Robin Vowels [robi...@do
Vowels [robi...@dodo.com.au]
Sent: Friday, April 15, 2022 5:08 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
- Original Message -
From: "Tom Harper"
To:
Sent: Friday, April 15, 2022 3:06 AM
IMHO, the next instruction to add to z/Architecture w
Robin,
See embedded remarks.
Tom
Sent from my iPhone
> On Apr 15, 2022, at 5:08 AM, Robin Vowels wrote:
>
> - Original Message - From: "Tom Harper"
>
> To:
> Sent: Friday, April 15, 2022 3:06 AM
>
>
>> IMHO, the next instruction to add to z/Architecture would be an instruction
om.au]
> Sent: Friday, April 15, 2022 5:08 AM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: Next instruction needed
>
> - Original Message -
> From: "Tom Harper"
> To:
> Sent: Friday, April 15, 2022 3:06 AM
>
>
>> IMHO, the next in
instruction needed
- Original Message -
From: "Tom Harper"
To:
Sent: Friday, April 15, 2022 3:06 AM
> IMHO, the next instruction to add to z/Architecture would be an instruction
> to clear storage to
> zeros.
> Right now a number of methods are in widespread use, n
- Original Message -
From: "Tom Harper"
To:
Sent: Friday, April 15, 2022 3:06 AM
IMHO, the next instruction to add to z/Architecture would be an instruction to clear storage to
zeros.
Right now a number of methods are in widespread use, none of which are clean and simple. I mean,
On Apr 14, 2022, at 14:50:46, Tom Harper wrote:
>
> I did not propose any such instruction.
>
> Sent from my iPhone
>
>> On Apr 14, 2022, at 4:42 PM, Seymour J Metz wrote:
>>
>> You asked for an instruction to clear a page to zeros. I proposed an
>> instruction to clear a page to zeros witho
_
> From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on
> behalf of Tom Harper [tomhar...@phoenixsoftware.com]
> Sent: Thursday, April 14, 2022 3:46 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: Next instruction needed
>
> I don’t see what t
-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
I don’t see what this has to do with what I’m proposing.
Sent from my iPhone
> On Apr 14, 2022, at 3:39 PM, Seymour J Metz wrote:
>
> Not directly, but it also wouldn't prevent unnecessary page outs after page
> ste
behalf
of Keith Moe [ke...@sbcglobal.net]
Sent: Thursday, April 14, 2022 4:00 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
This already exists in the OS: PGSER RELEASE.
Keith Moe
BMC Software
Soon retired
On Thursday, April 14, 2022, 12:41:27 PM PDT, Seymour
whatever
>
>
> -Original Message-
> From: IBM Mainframe Assembler List On
> Behalf Of Tom Harper
> Sent: Thursday, April 14, 2022 12:06 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Next instruction needed
>
> IMHO, the next instruction to add to z/Arch
-LIST@LISTSERV.UGA.EDU
Subject: Next instruction needed
IMHO, the next instruction to add to z/Architecture would be an instruction to
clear storage to zeros.
Right now a number of methods are in widespread use, none of which are clean
and simple. I mean, it’s been almost sixty years.
MVCL takes three regi
MBLER-LIST@LISTSERV.UGA.EDU
Subject: Next instruction needed
IMHO, the next instruction to add to z/Architecture would be an instruction to
clear storage to zeros.
Right now a number of methods are in widespread use, none of which are clean
and simple. I mean, it’s been almost sixty years.
MVCL t
> behalf of Paul Gilmartin [0014e0e4a59b-dmarc-requ...@listserv.uga.edu]
> Sent: Thursday, April 14, 2022 1:26 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Re: Next instruction needed
>
>> On Apr 14, 2022, at 11:06:09, Tom Harper wrote:
>>
>> IMHO, the next i
-LIST@LISTSERV.UGA.EDU] on behalf
of Tom Harper [tomhar...@phoenixsoftware.com]
Sent: Thursday, April 14, 2022 1:06 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Next instruction needed
IMHO, the next instruction to add to z/Architecture would be an instruction to
clear storage to zeros.
Right now a numb
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Paul Gilmartin [0014e0e4a59b-dmarc-requ...@listserv.uga.edu]
Sent: Thursday, April 14, 2022 1:26 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Next instruction needed
On Apr 14, 2022, at 11:06:09, Tom H
I don’t believe the paging implications would be any different from an XC.
Sent from my iPhone
> On Apr 14, 2022, at 1:26 PM, Paul Gilmartin
> <0014e0e4a59b-dmarc-requ...@listserv.uga.edu> wrote:
>
> On Apr 14, 2022, at 11:06:09, Tom Harper wrote:
>>
>> IMHO, the next instruction to add t
: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Next instruction needed
Caution! This message was sent from outside your organization.
IMHO, the next instruction to add to z/Architecture would be an instruction to
clear storage to zeros.
Right now a number of methods are in widespread use, none of which are
On Apr 14, 2022, at 11:06:09, Tom Harper wrote:
>
> IMHO, the next instruction to add to z/Architecture would be an instruction
> to clear storage to zeros.
>
Would that cause a Lot of paging I/O? Would it be better to mark all pages as
invalid, to be cleared automatically when referenced, if
IMHO, the next instruction to add to z/Architecture would be an instruction to
clear storage to zeros.
Right now a number of methods are in widespread use, none of which are clean
and simple. I mean, it’s been almost sixty years.
MVCL takes three registers to set up beforehand; XC sets the co
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