frame Assembler List On Behalf
Of Farley, Peter x23353
Sent: Thursday, January 20, 2022 11:30 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
Note in that manual on page 34 of that PDF (page 6 in the book) it says:
When
Mainframe Assembler List On Behalf
Of Seymour J Metz
Sent: Thursday, January 20, 2022 12:18 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
Sorry; that should have been #page=33. On most browser that fragment will take
you t
From: IBM Mainframe Assembler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Kerry Liles [kerry.li...@gmail.com]
Sent: Thursday, January 20, 2022 11:45 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
Just FYI, that li
Dave Clark [dlcl...@winsupplyinc.com]
> Sent: Wednesday, January 19, 2022 5:20 PM
> To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
> Subject: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
>
> "IBM Mainframe Assembler List" wrote on
> 01/19/2022 05:12:36 PM
Shmuel wrote:
CLCL pair+pair (32)
CLCLE pair+pair (32 or 64)
CLCL should be "(32 or 64)" in this nomenclature.
Basically just about any instruction operand that is located by a register
(it could be via a register pair such as for CLCL, or just a
base-displacement with or without i
"IBM Mainframe Assembler List" wrote on
01/20/2022 03:17:17 AM:
> your initial request was for conversion of an unsigned 32-bit binary
value.
>
> The LGF you are using does sign extension... I'd suggest you use LLGF
> to avoid just that ;-)
Yes, it was. But I have to handle both sig
"IBM Mainframe Assembler List" wrote on
01/19/2022 08:42:25 PM:
> I strongly recommend sticking to standard linkage conventions, e.g.,
> R1 pointing to a PLIST that points to the binary and decimal fields.
If I were calling an external subroutine then that is exactly what
I would do.
"IBM Mainframe Assembler List" wrote on
01/20/2022 06:30:02 AM:
> Regardless of the instruction used to load the source register, CVD
treats
> it as a signed F-word. So any value with bit 32 (high-order bit of
lower
> half) on will be converted to a negative PD number. So,
That is t
Dave,
IIRC you are running in a pretty old VSE.
So here is something that occured to me when you asked for saving:
VSE 4.x had a very nasty habit of setting all high order words of grade
registers to FF on a path thru the dispatcher.
I found this when developing support for 64 bits for my
Regardless of the instruction used to load the source register, CVD treats
it as a signed F-word. So any value with bit 32 (high-order bit of lower
half) on will be converted to a negative PD number. So,
CVD R1,DWORD
IF LTR,R1,R1,M
AP DWORD,=P' 4294967296'
ENDIF
The modern ways are much bette
Dave,
your initial request was for conversion of an unsigned 32-bit binary value.
The LGF you are using does sign extension... I'd suggest you use LLGF
to avoid just that ;-)
Additionally, if speed is a concern, you might want to save only the
high halves of registers
when they may be changed d
@LISTSERV.UGA.EDU] on behalf
of Dave Clark [dlcl...@winsupplyinc.com]
Sent: Wednesday, January 19, 2022 4:48 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Unsigned Binary Formats
"IBM Mainframe Assembler List" wrote on
01/19/2022 12:58:23 PM:
> You can also swap out the first two
R-LIST@LISTSERV.UGA.EDU
Subject: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
"IBM Mainframe Assembler List" wrote on
01/19/2022 05:12:36 PM:
> Is register 2 considered volatile for the 64 bit high half?
>
> If not, then how do you know if the macro user w
: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
"IBM Mainframe Assembler List" wrote on
01/19/2022 05:12:36 PM:
> Is register 2 considered volatile for the 64 bit high half?
>
> If not, then how do you know if the macr
-LIST@LISTSERV.UGA.EDU]
On Behalf Of Dave Clark
Sent: Wednesday, January 19, 2022 2:21 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
"IBM Mainframe Assembler List" wrote on
01/19/2022 05:12:36 PM:
> Is reg
ices Guide.
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Dave Clark
Sent: Wednesday, January 19, 2022 4:21 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Saving Caller's 64-bit Regsiters (was: Unsigned Binary Formats)
"IBM Mainframe Assembler List" wrote
"IBM Mainframe Assembler List" wrote on
01/19/2022 05:12:36 PM:
> Is register 2 considered volatile for the 64 bit high half?
>
> If not, then how do you know if the macro user will preserve and
> restore the register?
There is no macro, but I think I get your point. Although testing
-LIST@LISTSERV.UGA.EDU
Subject: Re: Unsigned Binary Formats
"IBM Mainframe Assembler List" wrote on
01/19/2022 12:58:23 PM:
> You can also swap out the first two instructions below with...
>
> LLGF R2,bin4
OK, I have created a generic subroutine that always converts
64-
"IBM Mainframe Assembler List" wrote on
01/19/2022 12:58:23 PM:
> You can also swap out the first two instructions below with...
>
> LLGF R2,bin4
OK, I have created a generic subroutine that always converts
64-bit register 2 to a left-justified, separate-left-signed, zoned number
up
bject: Unsigned Binary Formats
If I have a 4-byte signed binary number (i.e., up to 2147483647),
I can convert it to packed format as follows.
LR2,BIN4
CVD R2,PWORK8
How would I convert a 4-byte --un--signed binary number (such as
an RBA, up to 4294967295) to packed format? If yo
Subject: Re: 64-bit registers (was: Unsigned Binary Formats)
Um yeah... for approximately 21 years.
sas
On Wed, Jan 19, 2022 at 1:45 PM Dave Clark wrote:
> "IBM Mainframe Assembler List" wrote on
> 01/19/2022 01:00:07 PM:
> > I'd suggest you clear the high-ord
"IBM Mainframe Assembler List" wrote on
01/19/2022 02:16:55 PM:
> Um yeah... for approximately 21 years.
>
> sas
Well those of us constantly on older hardware and told to code in
COBOL most of the time don't get to play as often with the newer assembler
stuff. ;-b
Sincerely,
Dav
mbler List [ASSEMBLER-LIST@LISTSERV.UGA.EDU] on behalf
of Dave Clark [dlcl...@winsupplyinc.com]
Sent: Wednesday, January 19, 2022 1:44 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: 64-bit registers (was: Unsigned Binary Formats)
"IBM Mainframe Assembler List" wrote on
01/19/2022 01:
Um yeah... for approximately 21 years.
sas
On Wed, Jan 19, 2022 at 1:45 PM Dave Clark wrote:
> "IBM Mainframe Assembler List" wrote on
> 01/19/2022 01:00:07 PM:
> > I'd suggest you clear the high-order word of R2 then use CVDG.
> >
> > Would that work for you?
>
> OK, that brings up a
-LIST@LISTSERV.UGA.EDU
Subject: 64-bit registers (was: Unsigned Binary Formats)
"IBM Mainframe Assembler List" wrote on
01/19/2022 01:00:07 PM:
> I'd suggest you clear the high-order word of R2 then use CVDG.
>
> Would that work for you?
OK, that brings up a questio
That's correct. Your greater the 4-byte arithmetic just got easier! If
you use them in an assembler subroutine, you should save the the
incoming 64-bit register and restore it on the way out. There are
details about only saving the high half and it not being necessary for
certain registers, but
:45 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: 64-bit registers (was: Unsigned Binary Formats)
"IBM Mainframe Assembler List" wrote on
01/19/2022 01:00:07 PM:
> I'd suggest you clear the high-order word of R2 then use CVDG.
>
> Would that work for you?
OK, that brings up
r seems to be around 10 times faster than CVD/UNPK, according
to my measurements on a z15 T02.
Robert Ngan
DXC Luxoft
-Original Message-
From: IBM Mainframe Assembler List On Behalf
Of Dave Clark
Sent: Wednesday, January 19, 2022 11:32
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Unsig
"IBM Mainframe Assembler List" wrote on
01/19/2022 01:00:07 PM:
> I'd suggest you clear the high-order word of R2 then use CVDG.
>
> Would that work for you?
OK, that brings up a question that I have not had to address
before this. Up till now I've used odd-even register pairs for 64-
Dave,
I'd suggest you clear the high-order word of R2 then use CVDG.
Would that work for you?
Kind regards,
Abe Kornelis
===
Op 19/01/2022 om 18:32 schreef Dave Clark:
> If I have a 4-byte signed binary number (i.e., up to 2147483647),
> I can convert it to packed format as f
: Re: Unsigned Binary Formats
Caution! This message was sent from outside your organization.
Off the top of my head:
SGR R2,R2
ICM R2,b'',bin4
CVDG R2,PWORK16
Tony Thigpen
Dave Clark wrote on 1/19/22 12:32 PM:
> If I have a 4-byte signed binary number (i.e., up to
>
Off the top of my head:
SGR R2,R2
ICM R2,b'',bin4
CVDG R2,PWORK16
Tony Thigpen
Dave Clark wrote on 1/19/22 12:32 PM:
If I have a 4-byte signed binary number (i.e., up to 2147483647),
I can convert it to packed format as follows.
LR2,BIN4
CVD R2,PWORK8
How w
Insert the unsigned 4 byte value in the right half of a zeroed 64-bit
register and use CVDG. There is also a CVBG.
On 2022-01-19 12:32 p.m., Dave Clark wrote:
If I have a 4-byte signed binary number (i.e., up to 2147483647),
I can convert it to packed format as follows.
LR2,BIN4
C
If I have a 4-byte signed binary number (i.e., up to 2147483647),
I can convert it to packed format as follows.
LR2,BIN4
CVD R2,PWORK8
How would I convert a 4-byte --un--signed binary number (such as
an RBA, up to 4294967295) to packed format? If you need a reason, I'm
wr
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