On Fri, Feb 08, 2013 at 02:02:20PM +0400, Alexander Shiyan wrote:
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
Applied this one for master.
Sascha
---
arch/arm/cpu/mmu.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/mmu.c
On Fri, Feb 08, 2013 at 10:28:44AM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Cc: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
arch/arm/boards/sama5d3xek/init.c | 31 +++
1 file changed, 31
On Fri, Feb 08, 2013 at 10:07:39AM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
HI,
This patch serie fixe more issue on the macb and add the GEM support
(gigabit support) present on Atmel sama5d3x as example
The IP version is detected as in linux
we now share
On Fri, Feb 08, 2013 at 02:02:13PM +0400, Alexander Shiyan wrote:
One lowlevel initialization will be used on any CLPS711X-target,
so move it in the common location.
Signed-off-by: Alexander Shiyan shc_w...@mail.ru
---
arch/arm/boards/clep7212/Makefile |3 +-
Cc: Sascha Hauer s.ha...@pengutronix.de
Cc: Steffen Trumtrar s.trumt...@pengutronix.de
Signed-off-by: Hubert Feurstein h.feurst...@gmail.com
---
Changes since V1:
- rebased on latest master with arm-entry changes
- use phy_register_fixup_for_uid to register phy fixup
- register SD4 as first
On Fri, Feb 08, 2013 at 11:20:49PM +0400, Alexander Shiyan wrote:
Subject: i.MX53: Add WEIM register defines ( same as i.MX51 )
Signed-off-by: George Pontis gpon...@spamcop.net
diff -Naur bb.a/arch/arm/mach-imx/include/mach/imx53-regs.h
Hi Xavier,
On Fri, Feb 08, 2013 at 03:01:53PM -0500, Xavier Douville wrote:
Hi
On my board I needed to pass a custom VID header offset to ubiattach.
This patch adds the required option to the barebox command.
I don't know exactly, but I suspect something is wrong on your board
then.
Hello.
...
diff --git a/arch/arm/boards/clep7212/Makefile
b/arch/arm/boards/clep7212/Makefile
index a63aeae..676e867 100644
--- a/arch/arm/boards/clep7212/Makefile
+++ b/arch/arm/boards/clep7212/Makefile
@@ -1,2 +1 @@
-obj-y += lowlevel.o clep7212.o
-pbl-y += lowlevel.o
+obj-y
On Sun, Feb 10, 2013 at 05:22:49PM +0100, Eric Bénard wrote:
- this patch fix MCI support and enable using the SDCard to store
the environment.
- it is fully copied from imx23-olinuxino.c
- tested on i.MX23 EVK RevB1
Signed-off-by: Eric Bénard e...@eukrea.com
Applied this series.
BTW you
On Fri, Feb 08, 2013 at 10:07:01PM +0400, Alexander Shiyan wrote:
device_platform_driver() - Helper macro for drivers that don't do
anything special in module registration. This eliminates a lot of
boilerplate. Driver registration will called on device_initcall.
Signed-off-by: Alexander
On Mon, Feb 11, 2013 at 01:30:53PM +0400, Alexander Shiyan wrote:
Hello.
...
diff --git a/arch/arm/boards/clep7212/Makefile
b/arch/arm/boards/clep7212/Makefile
index a63aeae..676e867 100644
--- a/arch/arm/boards/clep7212/Makefile
+++ b/arch/arm/boards/clep7212/Makefile
@@
On Sun, Feb 10, 2013 at 05:58:56PM +0100, Vicente Bergas wrote:
Add the initrd start and end address to the DT, code comes from u-boot.
Signed-off-by: Vicente Bergas vice...@gmail.com
---
arch/arm/lib/armlinux.c | 2 ++
common/oftree.c | 66
On Fri, Feb 08, 2013 at 09:55:50AM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Due to a hw bug do not enable teh Asym_Pause.
Otherwise if you ser the bit 11 in 4h you will have to unplug
and replug the cable to make the phy work.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
On Fri, Feb 08, 2013 at 04:22:09PM +0100, Jan Weitzel wrote:
Hi,
with the release v2013.02.0 the MLO gets so bit, that it eats the boot
information in the SRAM.
nm --size-sort
...
0630 D nand_flash_ids
08c0 t mci_probe
0c00 b gpio_desc
1400 b files
If I remove
The default setting for the imx28 watchdog is to do a power-off reset. If the
SoC is only powered via battery, then the watchdog powers the chip down, though.
According to the datasheet it should still be possible to execute a proper POR
with battery power, but testing showed otherwise.
When the
On 09:30 Mon 11 Feb , Sascha Hauer wrote:
On Fri, Feb 08, 2013 at 10:28:44AM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Cc: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
arch/arm/boards/sama5d3xek/init.c | 31
Hi,
The following changes since commit e43e1498f65fe03cfc6b2744247eeccf27b26876:
MIPS: pbl: fix none compression support (2013-02-05 09:43:17 +0100)
are available in the git repository at:
git://git.jcrosoft.org/barebox.git delivery/vexpress
for you to fetch changes up to
so we can detect
ARM920
ARM926
ARM1176
PXA250
PXA255
PXA270
Cortex-A8
Cortex-A5
Cortex-A7
Cortex-A9
Cortex-A15
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
arch/arm/include/asm/system_info.h | 63
1 file changed, 63
detect the cpu model to dynamise the periphs mapping
currently only tested on qemu but should work on real hardware
Cortex-A9
if you use 1GiB of ram you can run the same barebox on Cortex-A15 or Cortex-A9
otherwise use vexpress_ca9_defconfig where the TEXT_BASE is at 0x63f0
when we will
On Mon, Feb 11, 2013 at 12:35:19PM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
On 09:30 Mon 11 Feb , Sascha Hauer wrote:
On Fri, Feb 08, 2013 at 10:28:44AM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Cc: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Jean-Christophe
Hi
Sascha Hauer wrote:
I don't know exactly, but I suspect something is wrong on your board then. Normally the VID header offset should be detected correctly automatically. Does the kernel also need a special VID header offset? Have you flashed an UBI image or did you generate the UBI on the
On Mon, Feb 11, 2013 at 10:14:50AM -0500, Xavier Douville wrote:
Hi
Sascha Hauer wrote:
I don't know exactly, but I suspect something is wrong on your
board then. Normally the VID header offset should be detected
correctly automatically. Does the kernel also need a special VID
header
On Fri, Feb 08, 2013 at 10:18:49AM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
the mininal tx ring size is 2 as if one we wrap on the same descriptor
and can cause IP lock on GEM (gigabit version) this is always the case
Signed-off-by: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by:
On 17:33 Mon 11 Feb , Sascha Hauer wrote:
On Fri, Feb 08, 2013 at 10:18:49AM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
the mininal tx ring size is 2 as if one we wrap on the same descriptor
and can cause IP lock on GEM (gigabit version) this is always the case
Signed-off-by:
the mininal tx ring size is 2 as if one we wrap on the same descriptor
and can cause IP lock on GEM (gigabit version) this is always the case
Signed-off-by: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/macb.c | 48
based on the kernel code
detect it via IP version
In the GEM we can use a full packet buffer for receive but the buffer size
need to be 64bit size aligned.
Signed-off-by: Nicolas Ferre nicolas.fe...@atmel.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
arch/arm/cpu/cpu.c | 22 --
arch/arm/cpu/mmu.c | 15 ---
arch/arm/cpu/mmu.h |6 ++
3 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/cpu.c
Drop copy in cache-l2x0
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
arch/arm/cpu/cache-l2x0.c | 32 +---
arch/arm/include/asm/cache-l2x0.h | 150 +
2 files changed, 102 insertions(+), 80 deletions(-)
rewrite
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/ata/Kconfig|4
drivers/ata/Makefile |2 ++
drivers/ata/ahci-generic.c | 47
3 files changed, 53 insertions(+)
create mode 100644
From: Rob Herring rob.herr...@calxeda.com
Some Intel SSDs can send a COMINIT after the initial COMRESET. This causes
the link to go down and we need to re-initialize the link.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
Hi,
The following patch serie add the support of the Quad Core Cortex-A9
Highbank from Calxeda
As I do not have the real hardware this is only tested on qemu
Rob could confirm if this work on real hw
This patch serie depends on the amba sp804 patch and
Cc: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/net/Kconfig |3 +
drivers/net/Makefile |1 +
drivers/net/xgmac.c | 731 ++
3 files changed, 735 insertions(+)
Hi,
v2:
fix cc tag so Rob can receive the patch
add oftree support to xgmac
The following patch serie add the support of the Quad Core Cortex-A9
Highbank from Calxeda
As I do not have the real hardware this is only tested on qemu
Rob
currently only tested under qemu
qemu-system-arm -M highbank -nographic -m 4089 -kernel
build/highbank/arch/arm/pbl/zbarebox -tftp . -drive
id=disk,if=ide,file=disk.img -device ide-drive,drive=disk,bus=ide.0
with:
- timer (AMBA SP804)
- uart (AMBA PL011)
- gpio (AMBA PL061)
- ahci
- net
not enable as on qemu this generate a undefined instruction exception
Cc: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
arch/arm/Kconfig|1 +
arch/arm/mach-highbank/Makefile |1 +
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/amba/bus.c |1 +
drivers/of/base.c | 60 +---
2 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index
Hi Hubert,
On Mon, Feb 11, 2013 at 09:55:05AM +0100, Hubert Feurstein wrote:
Cc: Sascha Hauer s.ha...@pengutronix.de
Cc: Steffen Trumtrar s.trumt...@pengutronix.de
Signed-off-by: Hubert Feurstein h.feurst...@gmail.com
---
Changes since V1:
- rebased on latest master with arm-entry changes
On Mon, Feb 11, 2013 at 08:02:24PM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
in commit e118761c5f7e8
oftree command: refactor
the Kconfig CMD_OFTREE_PROBE was remove
Oops.
Applied, thanks
Sascha
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
On Mon, Feb 11, 2013 at 08:09:25PM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/amba/bus.c |1 +
drivers/of/base.c | 60
+---
2 files changed, 53
On 21:17 Mon 11 Feb , Sascha Hauer wrote:
On Mon, Feb 11, 2013 at 08:09:25PM +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
drivers/amba/bus.c |1 +
drivers/of/base.c | 60
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
---
v2: fix platform not platfrom
Best Regards,
J.
drivers/amba/bus.c |1 +
drivers/of/base.c | 60 +---
2 files changed, 53 insertions(+), 8 deletions(-)
diff --git
On ArchosG9 the second stage low-level init was the fallback default.
Now that the low-level init is forcibly enabled it has to be skipped
when already executed from first stage.
Signed-off-by: Vicente Bergas vice...@gmail.com
---
arch/arm/boards/archosg9/lowlevel.c | 7 +--
1 file
Here are the last two patches I've submitted.
The first is a straightforward solution to a regression.
The second was first intended to provide devicetree support for booting an
omap4 based tablet. I've achieved booting it successfully, but after several
tries at bringing the mmc controller
Hello.
On Fri, Feb 08, 2013 at 10:07:01PM +0400, Alexander Shiyan wrote:
device_platform_driver() - Helper macro for drivers that don't do
anything special in module registration. This eliminates a lot of
boilerplate. Driver registration will called on device_initcall.
Signed-off-by:
On Tue, Feb 12, 2013 at 12:13:06AM +0100, Alexander Aring wrote:
Hi Sascha,
On Mon, Feb 11, 2013 at 12:40:23PM +0100, Sascha Hauer wrote:
On Fri, Feb 08, 2013 at 12:02:20PM +0100, Alexander Aring wrote:
Hi Sascha,
On Fri, Feb 08, 2013 at 10:24:17AM +0100, Sascha Hauer wrote:
On Tue, Feb 12, 2013 at 10:57:09AM +0400, Alexander Shiyan wrote:
Hello.
On Fri, Feb 08, 2013 at 10:07:01PM +0400, Alexander Shiyan wrote:
device_platform_driver() - Helper macro for drivers that don't do
anything special in module registration. This eliminates a lot of
boilerplate.
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