Add the compatible for the Raspberry Pi AUX UART and an init function which
enables it via the aux register and configures the correct shift value.
Signed-off-by: Rouven Czerwinski
---
drivers/serial/serial_ns16550.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/
Since we now use the miniuart on the raspberry pi 3, the miniuart overlay is no
longer needed.
Signed-off-by: Rouven Czerwinski
---
Documentation/boards/bcm2835.rst | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/boards/bcm2835.rst b/Documentation/boards/bcm2835.rst
index 79ea0f
Since we now support the miniuart, enable it as the default stdout port.
With this change the device tree overlay to switch the miniuart to bluetooth is
no longer necessary.
Signed-off-by: Rouven Czerwinski
---
arch/arm/dts/bcm2837-rpi-3.dts | 7 +--
1 file changed, 1 insertion(+), 6 deletio
Since the 16550 driver now supports the RPI3 miniuart, enable it in the default
config.
Signed-off-by: Rouven Czerwinski
---
arch/arm/configs/rpi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/rpi_defconfig b/arch/arm/configs/rpi_defconfig
index 2bb6158..dc5ab1f 1
According to the device tree bindings for 8250, width is an optional property.
Default to 1 which is the same default value as used by the kernel.
Before this change the driver would not work for device trees which do not
include the optional binding.
Signed-off-by: Rouven Czerwinski
---
drivers
The miniuart uses the core clock as the clock source. This clock is fixed by the
firmware to 250Mhz if enable_uart=1 is set in the config.txt file.
However a user could still choose to overclock the core frequency,
which would result in wrong baudrates computed by barebox.
Retrieve the core clock f
This patch series adds support for the raspberry pi miniuart (also called
aux-uart) to barebox.
With this series the miniuart overlay is no longer necessary to start barebox on
Raspberry Pi 3.
v3:
- Fix Indentation
from Oleksij Rempel and Sascha Hauer
v2:
- Move console clock initialization int
We don't know if the firmware running on the raspberry pi is the same firmware
which is running on all bcm283x devices.
Therefore move the console clock initialization into the rpi-common.c board
file.
A future commit will use this function to retrieve the miniuart clock from the
raspberry pi firm
Hi Alexander,
On Mon, Dec 17, 2018 at 08:51:49AM +0300, Alexander Shiyan wrote:
> This is a cumulative patch for the Digi ConnectCore CCMX51 SOM.
> It includes:
> - Switch board to devicetree probe.
> - Add MMC update handler.
> - Switch to multiimage support.
> - Cleanup and optimize board code.
On Sat, Dec 15, 2018 at 11:02:34AM +0100, Oleksij Rempel wrote:
> According to COPYING file in the root directory, this files should be
> marked as GPL-1.0-or-later:
>
> 9. The Free Software Foundation may publish revised and/or new versions
> of the General Public License from time to time.
Port of a Linux commit 314fc854f50317931fb4dfaab431695ab886e8de
No functional change. Fix all checkpatch warnings and check errors in
pcie-designware.c
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Bjorn Helgaas
Acked-By: Joao Pinto
Signed-off-by: Andrey Smirnov
---
drivers
Port of a Linux commit 8bad7f2fc3006d1752c426343ca77f1fbe61cf00
Pass the struct imx6_pcie pointer, not dbi_base address, to PHY accessors.
This enables future simplifications. No functional change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-
Port of a Linux commit 9ab021b6cf8b5bfc40ea9333c9b64b554fe01cd4
Remove unused return values. No functional change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --gi
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index baa07447e..8e7bae258 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -289,20 +289,2
Port of a Linux commit caf3f562e1161a86bd48a4c4c33af89d3693c658
When a PCI card is not connected, the following messages are seen on mx6:
imx6q-pcie 1ffc000.pcie: phy link never came up
imx6q-pcie 1ffc000.pcie: Link never came up
The first one comes from the pcie-designware.c core fi
Port of a Linux commit c2deae44616dab0112d965a0dc72d053b5727b4b
The subordinate value indicates the highest bus number which can be
reached downstream though a certain device.
Commit a20c7f36bd3d ("PCI: Do not allocate more buses than available in
parent")
ensures that downstream device
Port of a Linux commit d91dfe5054d4f2c424bd70ca34fc3328ee179f20
dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt
Pin registers, but the fixes don't actually work because these registers
are read-only.
Enable write permission before updating the Class Code and Inter
Port of a Linux commit a509d7d9af5ebf86ffbefa98e49761d813fb1d40
Previously dbi accessors can be used to access data of size 4 bytes. But
there might be situations (like accessing MSI_MESSAGE_CONTROL in order to
set/get the number of required MSI interrupts in EP mode) where dbi
accessors m
Port of a Linux commit a5fcec480f25eb5444c0b71ecdf9b18b09236b95
Freescale has stated [1] that the LVDS clock source of the IMX6 does not
pass the PCI Gen2 clock jitter test, therefore unless an external Gen2
compliant external clock source is present and supplied back to the IMX6
PCIe core
Port of a Linux commit b50b2db266d8a8c303e8d88590c6416dfe576c6c
dwc has 2 dbi address space labeled dbics and dbics2. The existing helper
to access dbi address space can access only dbics. However dbics2 has to
be accessed for programming the BAR registers in the case of EP mode. This
is i
Port of a Linux commit edd45e3968299f9b4635bdfeca1edab842d81eac
No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to
dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these
functions are used to perform only outbound configurations. Also move
these _unr
Port of a Linux commit feb85d9b1c47ea8dbcae559ff127b433fdb245b7
Split pcie-designware.c into pcie-designware-host.c that contains the host
specific parts of the driver and pcie-designware.c that contains the parts
used by both host driver and endpoint driver.
Signed-off-by: Kishon Vijay A
Port of a Linux commit 684a3a91da401195dbe33b7cef9472bca41c61b9
Helper functions dw_pcie_prog_*_atu_unroll() don't need to be in global
scope, so make them static.
Cleans up sparse warnings:
- symbol 'dw_pcie_prog_outbound_atu_unroll' was not declared. Should it be
static?
- symbol
Port of a Linux commit b4a8a51caf7de47c2fb03dfb1bbbe442661b5732
Replace of all initial lowercase character in comments and debug messages
to uppercase to maintain coherence.
Fix messages coherence within the DesignWare driver.
Fix code style on dw_pcie_irq_domain_free() function.
Sign
This patch revises the bits for register MC13892_POWER_MISC.
- Added definition for one missing bit (0).
- Changed the name for bit 21 for accordance with the datasheet.
- Updated affected board that uses these definitions.
- Replaced tabs with spaces for the remaining bits.
Signed-off-by: Ale
This is a cumulative patch for the Digi ConnectCore CCMX51 SOM.
It includes:
- Switch board to devicetree probe.
- Add MMC update handler.
- Switch to multiimage support.
- Cleanup and optimize board code.
Signed-off-by: Alexander Shiyan
---
arch/arm/Makefile |
Port of a Linux commit 7e00dfd0fbbb2fc276592613f76ded0b9a139a04
The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
allow a driver to override the default DesignWare register accessors.
Make the signature of the override functions the same as the default
accessors. Thi
Port of a Linux commit 442ec4c04d1235f8c664a74004dae54a7a574d18
Keep only the host-specific members in struct pcie_port and move the common
members (i.e common to both host and endpoint) to struct dw_pcie. This is
in preparation for adding endpoint mode support to designware driver.
Whil
Port of a Linux commit 5f334db665173facf2213854408bb5fa2445d0b3
The "num-lanes" DT property is parsed in dw_pcie_host_init(). However
num-lanes is applicable to both root complex mode and endpoint mode. As a
first step, move the parsing of this property outside dw_pcie_host_init().
This is
No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
anything specific to access configuration space. It can be just renamed to
dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Bjorn Helgaas
Port of a Linux commit e7d7705ace9494949863848ec77536d5a3287b0a
Only interfaces used from outside the driver, e.g., those called by
the DesignWare core, need to accept pointers to the generic struct
pcie_port. Internal interfaces can accept pointers to the
device-specific struct, whic
Port of a Linux commit 4a301766f5263dd94c1b95d1b1bbdf338afb1a37
In several dwc-based drivers, ->host_init() can fail, so make sure to
propagate and handle this to avoid continuing operation of a driver or
hardware in an invalid state.
Signed-off-by: Bjorn Andersson
Signed-off-by: Bjorn
Port of a Linux commit 96291d565550c1fd363e488cc17cb3189d2e4cc2
Fix various typos and whitespace errors:
s/Synopsis/Synopsys/
s/Designware/DesignWare/
s/Keystine/Keystone/
s/gpio/GPIO/
s/pcie/PCIe/
s/phy/PHY/
s/confgiruation/configuration/
No functional change int
Port of a Linux commit e9be4d78618af2e0d5592d9556cf0bba210cfd1a
The ATU CTRL2 register is 32 bits, and bits other than the enable bit may
be set. To check whether the ATU is enabled or not, we should test the
enable bit specifically.
Signed-off-by: Jisheng Zhang
Signed-off-by: Bjorn H
Port of a Linux commit 3d469939bcdf044d9f370be4f6bf21436afea310
The register accessors are not performance critical and small enough that
the compiler can inline them itself if it makes sense.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pcie-designware.c |
Port of a Linux commit f5acb5c51de2c073ee5f80d868354113ce0227ee
Swap order of dw_pcie_readl_unroll() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
Port of a Linux commit e44abfed6fcb750d24f4438dc9d5a02eebb5fcac
The read-only DBI registers can be written only when the "Write to RO
Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set.
Add accessors to enable and disable write permission, and use them instead
of acces
Port of a Linux commit 4ab2e7c0df6b8bbc6c8ea1617b737d33c2510012
The dw_pcie_host_ops structures are never modified. Constify these
structures such that these can be write-protected.
Signed-off-by: Jisheng Zhang
Signed-off-by: Bjorn Helgaas
Acked-by: Jingoo Han
Acked-by: Kishon Vij
Port of a Linux commit 6995de2168edc6e58a350e7eb76e02dd191b64f4
Replace a division by 2 operation for a right shift rotation of 1 bit.
Probably any recent and decent compiler does this kind of substitution
in order to improve code performance. Nevertheless it's a coding good
practice when
Port of a Linux commit 2a6a85d5368e55e506abd7ca79f08131028bb0bc
The dw_pcie_readl_rc() and dw_pcie_writel_rc() interfaces already add in
pp->dbi_base, so use those instead of doing it ourselves in the imx6
driver. No functional change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-b
Port of a Linux commmit b90dc392212d1153a12eea15cbc6eae352a3c989
No functional change. Move the register defines and other macros from
pcie-designware.c to pcie-designware.h. This is in preparation to split the
pcie-designware.c file into designware core file and host-specific file.
While
Port of a Linux commit 13957652f7242a8cb02ffb8c96f412f62c486ee1
Use a local "struct device *dev" for brevity and consistency with other
drivers. No functional change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 17 ++---
Port of a Linux commit 51c84709b8c4065fe83b84a487fe7822c2271e77
PCI: imx6: Removed unused struct imx6_pcie.mem_base
Removed the unused struct imx6_pcie.mem_base member. No functional change
intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6
Port of a Linux commit a71280722eeba8f1afa51ad6656028dcb96e110b
This causes CPU hangs when the system is reset by the watchdog, as the GPRs
aren't cleared, but the clocks are back to disabled state.
If the bootloader uses PCIe, it must take care to bring it down into a safe
state, before
Port of a Linux commit 8cfab3cf63cfe5a53e2e566b3b86b30c187edf3a
Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license.
Remove the boilerplate GPL version 2 language, relying on the assertion in
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to
fil
Port of a Linux commit 916bf1cc6528618197cdaf05ad42a9a82e9dea04
Reorder struct imx6_pcie to put generic fields first. No functional change
intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
Port of a Linux commit 40f67fb2c384fe12741aa35010d62bfe8c98286c
No functional change. Get device pointer at the beginning of
dw_pcie_host_init() instead of getting it all over dw_pcie_host_init().
This is in preparation for splitting struct pcie_port into host and core
structures (once spl
Port of a Linux commit 4d1821e729b5d2060ef8c9825af1dacc2182da38
Factor out ref clock enable to make it cleaner to add imx6sx support. No
functional change intended.
Signed-off-by: Bjorn Helgaas
Tested-by: Christoph Fritz
Signed-off-by: Andrey Smirnov
---
drivers/pci/pci-imx6.c | 43
Port of a Linux commit a0601a47053714eecec726aea5ebcd829f817497
Add support for the new iATU Unroll mechanism that will be used from Core
version 4.80. The new Cores can support either iATU Unroll or the "old"
iATU method, now called Legacy Mode. The driver is perfectly capable of
perfor
Port of a Linux commit a782b5f986c3fa1cfa7f2b57941200c6a5809242
Previously we checked for iATU unroll support by reading PCIE_ATU_VIEWPORT
even on platforms, e.g., Keystone, that do not have ATU ports. This can
cause bad behavior such as asynchronous external aborts:
OF: PCI: MEM 0x6
Port of a Linux commit fe48cb8538421fbd16ecf8bf95829faf8d8c001e
Most of the platforms have 3 or more viewports. For such platforms, We do
not need to share viewports between IO and CFG. Assign viewport 2 to IO
transactions in such cases.
Tested-by: Dong Bo
Signed-off-by: Pratyush Ana
Port of a Linux commit 67de2dc34cc30d334cb66ab4f466e80f04d5b618
Drivers based on the DesignWare core can override the config read accessors
by supplying rd_own_conf() and rd_other_conf() function pointers.
dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root
bus) or dw_p
Port of a Linux commit a5cb903aef8c642e6f0f6810d46dacedf666b54a
Currently dw_pcie_setup_rc() configures memory base and memory limit in the
type1 configuration header for the root complex. In doing so it uses the
CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
T
Port of a Linux commit 7e57fd1444bf8f4ba9179f826ed6817c56b801d4
dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates
IRQ domains, and enumerates devices below the bridge. dw_pcie_setup_rc()
programs the Root Complex registers. The Root Complex may lose power
during
Port of a Linux commit 446fc23fb6f0cab15011d7daae856091856a65cc
dw_pcie_readl_rc() reads a u32 value. Previously we stored that value in
space supplied by the caller. Return the u32 value directly instead.
This makes the calling code read better and makes it obvious that the
caller need
Port of Linux commit a26e0108b61d6e65c151af720f2c4248a38f000d
dw_pcie_readl_unroll() and dw_pcie_writel_unroll() duplicate what
dw_pcie_readl_rc() and dw_pcie_writel_rc() already do, so call them
directly.
[bhelgaas: reworked into patch series]
Signed-off-by: Kishon Vijay Abraham I
S
Export dw_pcie_readl_rc() and dw_pcie_writel_rc(). Many other drivers can
use these instead of implementing their own versions. No functional change
intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
---
drivers/pci/pcie-designware.c | 4 ++--
drivers/pci/pcie-desig
Port of a Linux commit ad8802189426cf7b3a2ad0444f71981fb81312a8
Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val"
order used by pci_write_config_word() and other drivers. No functional
change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
-
Port of a Linux commit c388de1c4f0e5da3e96b49efb0388e2a0d34e079
Move the link wait sleep definitions to the .c file as suggested by
Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto
Signed-off-by: Bjorn Helgaas
CC: Jisheng Zhang
Signed-off-by: Andrey Smirnov
---
drivers
Port of a Linux commit 68a0bfec72cb4f117198ae31df114dad4c5e405d
When we have only two view ports in a DesignWare PCIe platform, iatu0
is used for both CFG and IO accesses. When CFGs are sent to peripherals
(e.g., lspci), iatu0 frequently switches between CFG and IO.
For such scenarios, a
Port of a Linux commit 1034023606d0e971f4dee6f725e441b785a846b5
Rename dw_pcie_valid_config() to dw_pcie_valid_device() and use the result
directly as a boolean value instead of testing against 0. No functional
change intended.
Signed-off-by: Bjorn Helgaas
Signed-off-by: Andrey Smirnov
Port of a Linux commit 01c076732e8288485c22ef50f20949455a783ca9
The link may be up but still in link training. In this case, we can't
think the link is up and operating correctly. Teach dw_pcie_link_up() to
be aware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
Also rewrite PCIE_PHY_DE
Port of a Linux commit d8bbeb39fbf3ff06b6adae9d336f44bee4e3f3ec
Add a loop with timeout to make sure the iATU is really enabled before
subsequent config and I/O accesses.
[bhelgaas: split to separate patch, use dev_err() instead of dev_dbg()]
Signed-off-by: Joao Pinto
Signed-off-by: Bj
Port of a Linux commit dac29e6c5460d05774e3e8c4fdf4d6e7bd481fab
Add a default DesignWare "link_up" test for use when a sub-driver doesn't
supply its own pcie_host_ops.link_up() method.
[bhelgaas: changelog, split into its own patch]
Signed-off-by: Joao Pinto
Signed-off-by: Bjorn Helgaa
Port of a Linux commit 907fce0902539ecde609e485eb2ecd7119a7a623
Currently "num-lanes" is read in dw_pcie_host_init(), but it is only used
if we call dw_pcie_setup_rc() while bringing up the link. If the link has
already been brought up by firmware, we need not call dw_pcie_setup_rc(),
and
Port of Linux commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32
Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
spear13xx) had similar loops waiting for the link to come up.
Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
waiting is done
Port of a Linux commit 4d107d3b5a686b5834e533a00b73bf7b1cf59df7
imx6_pcie_link_up() previously used usleep_range() to wait for the link to
come up. Since it may be called while holding the config spinlock, the
sleep causes a "BUG: scheduling while atomic" error.
Instead of waiting for th
Port of a Linux commit dd193929d91e1b44b90f81509feeff10c94ddc4d
Some platforms don't support ATU, e.g., pci-keystone.c. These platforms
use their own address translation component rather than ATU, and they
provide the rd_other_conf and wr_other_conf methods to program the
translation comp
Port of a Linux commit 17209dfb35a228e597a387bfc83b68093b247f78
Read back the ATU CR2 register to ensure ATU programming is effective
before any subsequent I/O or config space accesses.
Without this, PCI device enumeration is unreliable.
[bhelgaas: changelog, comment]
Signed-off-by: St
Port of a Linux commit b6b18f589e1ddbfbc31f72ea7fb8a723a2d10058
Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and
dw_pcie_cfg_write(). These checks make sure that accesses are aligned on
their size, e.g., a 4-byte config access is aligned on a 4-byte boundary.
[bhelga
Port of a Linux commit 116a489d78b30862a2dd04961d3ba98fe4704220
Return values immediately when possible to simplify the control flow.
No functional change intended. Folded in unused variable removal as
pointed out by Fabio Estevam , Arnd Bergmann
, and Thierry Reding .
Signed-off-by:
Port of a Linux commit c003ca99632e1783466f459033874a0e1e31457b
dw_pcie_cfg_write() uses the exact 8-, 16-, or 32-bit access size
requested, but dw_pcie_cfg_read() previously performed a 32-bit read and
masked out the bits requested.
Use the exact access size in dw_pcie_cfg_read(). For e
Port of a Linux commit 2d91b491d5be13602a73be789bb8a3c28d06b7f2
Most transactions' type are cfg0 and MEM, so the current iATU usage is not
balanced: iATU0 is hot while iATU1 is rarely used.
Refactor the iATU usage so we use iATU0 for cfg and IO and iATU1 for MEM.
This allocation idea come
Signed-off-by: Andrey Smirnov
---
drivers/pci/pcie-designware.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pci/pcie-designware.h b/drivers/pci/pcie-designware.h
index 8d0330a5a..ba5752ec1 100644
--- a/drivers/pci/pcie-designware.h
+++ b/drivers/pci/pcie-designware.h
@@ -62,8 +62
Port of a Linux commit 63503c87f06e0f2c8c951cada81221c5500188d8
Currently, the outbound iATU programming functions are similar: the only
difference is index, type, addr and size. Consolidate these functions into
one. This saves about 1700 bytes in text:
textdata bss dec
Port of a Linux commit 4c45852f494dab827291c656ee9e12f3f4ee64d6
Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
split the address into "addr" and "where". The callees assumed "addr" was
32-bit aligned (with zeros in the low two bits) and they used only the low
two
Everyone:
As a part of working on adding support for PCI on i.MX7D/8MQ, I spent
some time looking through Linux commit history of pci-imx6.c and
pcie-designware*.c and porting various patches to minimize the
differences between the two codebases. This series is the result of
that effort. All of th
Port of a Linux commit ed8b472df44af6dc4cb18e828dc9bb2d57f14b9e
The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. In IP
v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8]
are defined for NUM_OF_LANES, bits [16:13] are for other usages (bit 16 is
AU
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