Hello Sascha,
On 24.02.21 09:49, Sascha Hauer wrote:
> On Tue, Feb 23, 2021 at 08:24:26AM +0100, Ahmad Fatoum wrote:
>> This ports over Linux commit 3ce120b16cc5 ("kbuild: add
>> '-fno-stack-check' to kernel build options"):
>>
>> Author: Linus Torvalds
>>
>> kbuild: add '-fno-stack-che
Hello Antony,
On 16.03.21 15:12, Antony Pavlov wrote:
> On Tue, 16 Mar 2021 09:04:59 +0100
> Ahmad Fatoum wrote:
>
>> We now have everything in place to migrate erizo to PBL.
>> As currently, this is the only board, we can drop all non-PBL support
>> in the same go.
>>
>> The board still throws
On Tue, 16 Mar 2021 09:04:59 +0100
Ahmad Fatoum wrote:
> We now have everything in place to migrate erizo to PBL.
> As currently, this is the only board, we can drop all non-PBL support
> in the same go.
>
> The board still throws TLSF errors on startup, but that was the case
> before the rework
Give the user information about the faulty block when an erase
operation fails with error.
Signed-off-by: Stefan Riedmueller
---
drivers/mtd/core.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/core.c b/drivers/mtd/core.c
index af33ad665c5a..22eb2a056c4e 100
Currently the nand-mxs driver uses a hook function to the
mtd->_block_markbad function to allow write access to the OOB bytes only
if it is to mark a block as bad.
This hook is not called when a Bad Block Table block is marked bad since
this routine directly calls nand_markbad_bbm.
The chip->lega
Let cdev_mount_default return an error in case the device is already
mounted to a different location than the default mount point.
Otherwise the automount routine can get stuck in an infinite loop
spamming:
mounted /dev/mmc0.0 on /mnt/mmc
mounted /dev/mmc0.0 on /mnt/mmc
mounted /dev/mmc0.0 on /mn
The blocks containing the bad block table can become bad as well. So
make sure to skip any blocks that are marked bad when searching for the
bad block table.
Signed-off-by: Stefan Riedmueller
---
drivers/mtd/nand/nand_bbt.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand
The STM32MP157A-EV1 and STM32MP157C-EV1 Evaluation boards are the
full-feature demonstration and development platforms for
STMicroelectronics Arm®-based dual Cortex®-A7 32 bits and
Cortex®-M4 32 bits MPUs in the STM32MP1 Series.
Add support for running barebox as SSBL on either of them.
Signed-of
This imports following Linux patches by Amelie Delaunay
:
phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivation
phy: stm32: replace regulator_bulk* by multiple regulator_*
phy: stm32: ensure pll is disabled before phys creation
phy: stm32: ensure phy are no more active whe
We have had all parts in place to use the OTG port on the STM32MP1
boards for a while now. Enable it in the defconfig. USB EHCI
has a driver, but still needs some glue, however.
Signed-off-by: Ahmad Fatoum
---
arch/arm/configs/stm32mp_defconfig | 8 +++-
1 file changed, 7 insertions(+), 1 de
GCC whines about casting int to pointer, which aren't always the same
size in barebox. Use long instead to avoid the warning.
Signed-off-by: Ahmad Fatoum
---
commands/bthread.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/commands/bthread.c b/commands/bthread.c
On Tue, Mar 16, 2021 at 08:03:01AM +, Denis Osterland-Heim wrote:
> Hi Sascha,
>
> Am Montag, den 15.03.2021, 09:04 +0100 schrieb Sascha Hauer:
> > Hi Denis,
> >
> > On Fri, Mar 12, 2021 at 02:39:40PM +, Denis Osterland-Heim wrote:
> > > Hi,
> > >
> > > It would be no problem to do it in a
From: Rouven Czerwinski
As our assembly routines are now written to work correctly on 32-bit as
well as 64-bit, nothing is holding us back from adding 64-bit support.
Signed-off-by: Rouven Czerwinski
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Kconfig | 27 +++--
From: Rouven Czerwinski
The generic dt board added in a previous commit can be booted on RISC-V
qemu -M virt. Add defconfigs for both 32- and 64-bit machines.
We could in theory drop the mach directory altogether like it's done on
arm64, but for now it's left in as it provides .
It's expected t
This barebox image implements the same header as Linux and receives
the device tree in the same register. It can be booted from barebox
or loaded by Qemu -kernel option.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Kconfig | 9
arch/riscv/boot/Makefile | 1 +
a
Make debugging a bit more convenient by providing users the option to
include symbol names.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4a2a547a7b35..91e8546f9624 100644
--- a/arch/riscv/Kcon
In preparation for migrating to PBL for RISC-V platforms, move the only
existing board support to a new arch/riscv/boards/ directory.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Makefile | 2 +-
arch/riscv/boards/Makefile| 2 ++
For non-NMON enabled board the RISC-V specific settings menu will be
empty. Improve UI/UX by adding something there.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Kconfig | 7 ++
arch/riscv/include/asm/string.h | 21 +-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/mem
Define some stubs, so we can get virtio MMIO working on RISC-V
in QEMU. As we don't yet have MMU support, this is sufficient.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/dma.h | 44
include/dma.h
While HW can emulate unaligned accesses at a performance penalty,
it's probably best to just not generate them.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/include/asm/unaligned.h | 16
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/include/asm/unaligne
-pipe -Wall is specified in top-level Makefile. Disabling warnings is
unneeded on the arch and is a left-over from MIPS port probably.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Makefile | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makef
The assembly putc routines do accesses the same size of the register
stride. Do likewise for the C implementation.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/include/asm/debug_ll_ns16550.h | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/include/as
Other architectures would benefit from the generic DT image too.
Add a new arch-agnostic symbol that arches besides ARM can select.
The new symbol itself should not have a prompt as the help text for
each architecture likely differs (e.g. device tree handoff register).
Signed-off-by: Ahmad Fatoum
Given that we only support a single RISC-V board, this puts us in
a good position to make this a multi-image-only architecture.
This commit adds the necessary bits. It's highly inspired by the ARM PBL
support. Notable difference is that for relocations to be generated, it
was necessary to compile
We now have everything in place to migrate erizo to PBL.
As currently, this is the only board, we can drop all non-PBL support
in the same go.
The board still throws TLSF errors on startup, but that was the case
before the rework as well. Tested with qemu as described in the docs.
Cc: Antony Pavl
CLINT is used by Linux selects on nommu RISC-V machines, while
the RISC-V timer with SBI is selected on MMU enabled ones.
Both are also available on the Qemu Virt machine, but only SBI
is available on TinyEmu. As we'll add Virt support in a follow-up
commit, import both drivers now. Erizo could in
The 1: is a left-over from before 5f04e5e03e94 ("ARM: aarch64: Fix
get_runtime_offset after relocation"). It's unused now, so drop it.
Signed-off-by: Ahmad Fatoum
---
arch/arm/lib64/runtime-offset.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib64/runtime-offset
VIRTIO has multiple backends, each with is its own dependencies.
It's thus wrong to select it from drivers. Fix this.
Signed-off-by: Ahmad Fatoum
---
drivers/serial/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 0
Many SoC reset/poweroff mechanisms can be represented using this generic
binding. Of the boards we support, at least the virt machines can
be rebooted and powered off by it. Import the Linux v5.11 state
of the driver to support this.
Signed-off-by: Ahmad Fatoum
---
arch/riscv/Kconfig
We still have no boot support for RISC-V, take the first step by
enabling barebox to detect a RISC-V Linux kernel image. The header
format is aligned with that of arm64.
Signed-off-by: Ahmad Fatoum
---
common/filetype.c | 3 +++
include/filetype.h | 1 +
2 files changed, 4 insertions(+)
diff -
With these changes applied, barebox can now generate images that can
be booted on qemu/tinyemu virt32 and virt64 machines.
The boards have clocksource, virtio, cfi-flash, reboot and poweroff
support.
This can also be pulled from Github:
https://github.com/a3f/barebox/tree/multi-image-riscv-v2
v
While block drivers may do DMA, they always use block caching chunks as
bounce buffer. No dma is every done directly to the block_read data
argument, so it doesn't need to be allocated with dma_alloc. The buffer
also need not be zeroed, as block_read will either overwrite it
completely or fail.
Si
Other PBL-enabled architecture can benefit from compressed dtbs as well.
Move symbol and code to a comm place to be able to use it from RISC-V
in a later commit. In order not to break out of tree boards at runtime,
the old symbol name is maintained for ARM.
Signed-off-by: Ahmad Fatoum
---
arch/a
Hi Sascha,
Am Montag, den 15.03.2021, 09:04 +0100 schrieb Sascha Hauer:
> Hi Denis,
>
> On Fri, Mar 12, 2021 at 02:39:40PM +, Denis Osterland-Heim wrote:
> > Hi,
> >
> > It would be no problem to do it in a script.
> > I did it as a fist prove of concept.
> > My opinion is, that this hard code
34 matches
Mail list logo
