Re: [PATCH v1] mci: add Marvell Dove SDHCI driver

On 11.04.2017 00:21, Michael Grzeschik wrote: From: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> This adds a driver for the SDHCI controller found on Marvell Dove SoCs. Despite a missing pinctrl driver, corresponding MPP config has to be set on a per board basis. This

Re: [PATCH v2] kwboot: do a filetype check before sending the image

On 01/20/2016 09:15 AM, Uwe Kleine-König wrote: The images that can be sent to a Marvell CPU have a fixed format. Do some sanity checks before actually sending an image for easier diagnosis of broken files. Signed-off-by: Uwe Kleine-König --- Changes since (implicit)

[PATCH v2 04/19] arm: pxa: Add clock for Zylonite NFC

Add a clock with clk_add_physbase for the NAND flash controller on Zylonite board. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- arch/arm/boards/zylonite/board.c | 7 +++ 1 file changed, 7 inserti

[PATCH v2 12/19] mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths

Newer versions of Marvell PXA3xx NFC also support BCH and therefore higher ECC strengths than 1. Prepare for different ECC strength by factoring out ECC init into separate functions by strength. Also, add a new host variable that indicates BCH ECC. Signed-off-by: Sebastian Hesselbarth

[PATCH v2 08/19] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

timeout values. Using the Auto Read Status feature prevents timeout issues on the two operations with none or wrong timing register setup. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- driv

[PATCH v2 14/19] mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC

Add support for 4bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- drivers/mtd/nand/nand_mrvl_nfc.c | 65 1 file

[PATCH v2 00/19] Armada 370/XP NAND driver

with Robert's patiently confirmed Tested-by on mach-pxa. I have tested this on IX4. Sebastian Hesselbarth (19): of: mtd: Import of_get_nand_ecc_{step_size,strength} from Linux mtd: nand: Clarify Marvell Orion Kconfig prompt arm: pxa: Prepare for NAND clkdev lookup on PXA3xx arm: pxa: Add

[PATCH v2 03/19] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx

To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP, prepare to provide a common clock for the NAND driver on PXA3xx. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Acked-by: Robert Jarzmik <robert.jarz...@free.fr> Tested-by: Robert Jarzmik

[PATCH v2 15/19] mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC

Add support for 8bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- drivers/mtd/nand/nand_mrvl_nfc.c | 39 +++ 1 file

[PATCH v2 02/19] mtd: nand: Clarify Marvell Orion Kconfig prompt

Kconfig prompt for Marvell Orion SoCs is missing a "Marvell" prefix, add it to the prompt. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- drivers/mtd/nand/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/K

[PATCH v2 13/19] mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions

Marvell PXA3xx NAND flash controller IP has been reused in later SoCs with additional HW features. Add HW BCH ECC as the first known HW difference. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- driv

[PATCH v2 06/19] arm: pxa: Remove pxa_get_nandclk()

With a common clock provided for NAND controller, get rid of the mach/clock.h way of getting the NAND clock. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Acked-by: Robert Jarzmik <robert.jarz...@free.fr> Tested-by: Robert Jarzmik <robert.jarz...@free.fr

[PATCH v2 11/19] mtd: nand_mrvl_nfc: Get ecc parameters from DT

With DT helpers for ECC step size and strength, now use them on Marvell NAND driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- drivers/mtd/nand/nand_mrvl_nfc.c | 8 1 file changed, 8 inserti

[PATCH v2 01/19] of: mtd: Import of_get_nand_ecc_{step_size, strength} from Linux

This imports DT helpers for MTD ECC step size and strength from Linux kernel. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- drivers/of/of_mtd.c | 34 ++ include/of_mtd.h| 2 ++ 2 files changed, 36 insertions(+) diff

[PATCH v2 10/19] mtd: nand_mrvl_nfc: Fix num-cs property parsing

The "num-cs" property does not encode flashes CS line but number of available CS signals. Fix wrong property parsing to ->cs by adding proper ->num_cs variable to host struct. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik &

[PATCH v2 05/19] mtd: nand_mrvl_nfc: Use common clock for core clock

With PXA3xx now providing a common clock for the NAND clock, use it and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP to reuse the same driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Acked-by: Robert Jarzmik <robert.jarz...@free.f

[PATCH v2 17/19] mtd: nand_mrvl_nfc: Add support for NDCB3 register

Newer versions of PXA3xx NAND controller support a 4th Command Buffer register. Add the required HWFLAGS and additional write to NDCB0. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Acked-by: Robert Jarzmik <robert.jarz...@free.fr> Tested-by: Robert Jarzmik

[PATCH v2 07/19] mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00

If OOB data is not required on page program, we have to clear the corresponding data with 0xff instead of 0x00. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Acked-by: Robert Jarzmik <robert.jarz...@free.fr> Tested-by: Robert Jarzmik <robert.jarz...@free.f

[PATCH v2 09/19] mtd: nand_mrvl_nfc: Protect mrvl_nand_probe_dt

Parsing DT nodes if CONFIG_OFTREE isn't enabled is pointless, also we should prefer potential platform_data passed earlier. Protect mrvl_nand_probe_dt by bailing out early if either CONFIG_OFTREE is not enabled or dev's platform_data is non-NULL. Signed-off-by: Sebastian Hesselbarth

[PATCH v2 18/19] mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP

Marvell PXA3xx and Armada 370/XP share the same NAND controller IP with some minor differences. With support for controller IP v2, now allow to build the driver on Armada 370/XP. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Acked-by: Robert Jarzmik <ro

[PATCH v2 19/19] mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U

This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- drivers/mtd/nand/nand_mrvl_nfc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/driv

[PATCH v2 16/19] mtd: nand_mrvl_nfc: Add support for HW BCH ECC

Add support for HW BCH ECC for those HW versions that support it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Tested-by: Robert Jarzmik <robert.jarz...@free.fr> --- drivers/mtd/nand/nand_mrvl_nfc.c | 26 +- 1 file changed, 25 inse

Re: [PATCH 00/17] Armada 370/XP NAND driver

On 20.10.2015 21:25, Robert Jarzmik wrote: > Robert Jarzmik <robert.jarz...@free.fr> writes: > >> Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: >> >>> Robert, >>> >>> I pushed another version of the patch set with

Re: [PATCH 00/17] Armada 370/XP NAND driver

On 16.10.2015 20:40, Robert Jarzmik wrote: It's this part with match which is NULL in my case: const struct mrvl_nand_variant *variant = match->data; Ok. I now moved the of_match and variant assignment below the OF protection. New version at the same branch. Sebastian

Re: [PATCH 2/3] scripts/kwbimage: Make BINARY files relative to config file

On 15.10.2015 11:00, Thomas Petazzoni wrote: On Thu, 15 Oct 2015 10:18:55 +0200, Sascha Hauer wrote: The BINARY files given in the config files are expected to be relative to the place kwbimage is called from. This is bad since it breaks where kwbimage is called from the build directory and not

Re: [PATCH 00/17] Armada 370/XP NAND driver

On 13.10.2015 12:38, Robert Jarzmik wrote: Sascha Hauer writes: In your temporary patch you have: @@ -67,6 +71,9 @@ static int zylonite_devices_init(void) _pdata); add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL,

Re: [PATCH] fs: Fix memcpy_sz for remaining count/rwsize

On 13.10.2015 10:00, Sascha Hauer wrote: On Mon, Oct 12, 2015 at 08:51:54PM +0200, Sebastian Hesselbarth wrote: On 12.10.2015 09:36, Sebastian Hesselbarth wrote: I used memcpy -s /mnt/image.img -d /dev/nand0.u-boot.bb 0 0 i.e. I did not specify any rwsize option. Looking at the code

Re: [PATCH 00/17] Armada 370/XP NAND driver

On 13.10.2015 11:35, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: On 12.10.2015 21:16, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: I have prepared a branch for you based on above v2015.10.0 to

Re: [PATCH 09/17] mtd: nand_mrvl_nfc: Get ecc parameters from DT

On 12.10.2015 08:28, Sascha Hauer wrote: On Sun, Oct 11, 2015 at 10:39:52PM +0200, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: With DT helpers for ECC step size and strength, now use them on Marvell NAND driver. Signed-off-by: Sebastian Hesse

Re: [PATCH] fs: Fix memcpy_sz for remaining count/rwsize

On 12.10.2015 08:11, Sascha Hauer wrote: On Thu, Oct 08, 2015 at 11:19:45PM +0200, Sebastian Hesselbarth wrote: When using memcpy_sz with rwsize != 1 integer division of count/rwsize may leave some bytes of the request uncopied if count is not a multiple of rwsize. Fix this behavior

[PATCH] of: mtd: Import of_get_nand_ecc_{step_size, strength} from Linux

This imports DT helpers for MTD ECC step size and strength from Linux kernel. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Cc: Ezeq

Re: [PATCH] fs: Fix memcpy_sz for remaining count/rwsize

On 12.10.2015 09:36, Sebastian Hesselbarth wrote: On 12.10.2015 08:11, Sascha Hauer wrote: On Thu, Oct 08, 2015 at 11:19:45PM +0200, Sebastian Hesselbarth wrote: When using memcpy_sz with rwsize != 1 integer division of count/rwsize may leave some bytes of the request uncopied if count

Re: [PATCH 00/17] Armada 370/XP NAND driver

On 12.10.2015 21:16, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: I have prepared a branch for you based on above v2015.10.0 to ease testing with all comments included so far: https://github.com/shesselba/barebox-dove.git testing/nfc-for-robert

Re: [PATCH 00/17] Armada 370/XP NAND driver

On 12.10.2015 12:38, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: This series is, of course, untested on mach-pxa and needs a Tested-by. I have tested the new driver on Armada XP based Lenovo ix4-300d and todays -next. I tested the parial

Re: [PATCH 15/17] mtd: nand_mrvl_nfc: Add support for NDCB3 register

On 10.10.2015 10:48, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: Newer versions of PXA3xx NAND controller support a 4th Command Buffer register. Add the required HWFLAGS and additional write to NDCB0. Signed-off-by: Sebastian Hesse

Re: [PATCH 07/17] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

On 10.10.2015 10:44, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: Marvell NAND controller allows to enable an Auto Read Status feature that will monitor NAND status during Erase and Program operations. Okay, I seem to remember barebox nand cor

Re: [PATCH 05/17] mtd: nand_mrvl_nfc: Remove keep_config

On 09.10.2015 21:16, Robert Jarzmik wrote: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> writes: keep_config and it's corresponding DT property is meant for the Linux kernel to keep the config setup by a boot-loader. As we are the bootloader and it is not used at all, g

[PATCH 09/17] mtd: nand_mrvl_nfc: Get ecc parameters from DT

With DT helpers for ECC step size and strength, now use them on Marvell NAND driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Cc: Ezeq

[PATCH 05/17] mtd: nand_mrvl_nfc: Remove keep_config

keep_config and it's corresponding DT property is meant for the Linux kernel to keep the config setup by a boot-loader. As we are the bootloader and it is not used at all, get rid of it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <ro

[PATCH 00/17] Armada 370/XP NAND driver

, the last patch adds optimized timings for the NAND flash found on Lenovo ix4-300d. This series is, of course, untested on mach-pxa and needs a Tested-by. I have tested the new driver on Armada XP based Lenovo ix4-300d and todays -next. Sebastian Hesselbarth (17): arm: pxa: Prepare for NAND clkdev

[PATCH 03/17] mtd: nand: Clarify Marvell Orion Kconfig prompt

Kconfig prompt for Marvell Orion SoCs is missing a "Marvell" prefix, add it to the prompt. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com>

[PATCH 08/17] mtd: nand_mrvl_nfc: Fix num-cs property parsing

The "num-cs" property does not encode flashes CS line but number of available CS signals. Fix wrong property parsing to ->cs by adding proper ->num_cs variable to host struct. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <r

[PATCH 02/17] mtd: nand_mrvl_nfc: Use common clock for core clock

With PXA3xx now providing a common clock for the NAND clock, use it and get rid of the mach/clock.h. This will allow Marvell Armada 370/XP to reuse the same driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr>

[PATCH 04/17] arm: pxa: Remove pxa_get_nandclk()

With a common clock provided for NAND controller, get rid of the mach/clock.h way of getting the NAND clock. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-el

[PATCH 01/17] arm: pxa: Prepare for NAND clkdev lookup on PXA3xx

To allow PXA3xx nand driver to be reused on Marvell Armada 370/XP, prepare to provide a common clock for the NAND driver on PXA3xx. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas

[PATCH] fs: Fix memcpy_sz for remaining count/rwsize

-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: barebox@lists.infradead.org --- fs/fs.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/fs/fs.c b/fs/fs.c index c041e41bb51b..ccbda22d2692 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -1580,9 +1580,7 @@ stati

[PATCH] clk: mvebu: Add corediv clock driver for Armada 370/XP

Newer Marvell MVEBU SoC like Armada 370/XP have an additional core clock divider for e.g. NAND clock. Add the corresponding driver based on the Linux driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Thomas Petazzoni <thomas.petazz...@free-electron

[PATCH] net: mvneta: add Armada XP compatible

Marvell NETA Network Engine found in Armada 370 and XP SoCs also has a different compatible for Armada XP. Add the compatible to the of_device_id list. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Thomas Petazzoni <thomas.petazz...@free-electron

[PATCH 15/17] mtd: nand_mrvl_nfc: Add support for NDCB3 register

Newer versions of PXA3xx NAND controller support a 4th Command Buffer register. Add the required HWFLAGS and additional write to NDCB0. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni &l

[PATCH 16/17] mtd: nand_mrvl_nfc: Add support for Marvell Armada 370/XP

Marvell PXA3xx and Armada 370/XP share the same NAND controller IP with some minor differences. With support for controller IP v2, now allow to build the driver on Armada 370/XP. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz..

[PATCH 11/17] mtd: nand_mrvl_nfc: Add hwflags to distinguish different HW versions

Marvell PXA3xx NAND flash controller IP has been reused in later SoCs with additional HW features. Add HW BCH ECC as the first known HW difference. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thom

[PATCH 13/17] mtd: nand_mrvl_nfc: Add support for 8bit BCH HW ECC

Add support for 8bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Cc: Ezequiel Garcia <ezequ...

[PATCH 06/17] mtd: nand_mrvl_nfc: Clear OOB data with 0xff instead of 0x00

If OOB data is not required on page program, we have to clear the corresponding data with 0xff instead of 0x00. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-el

[PATCH 12/17] mtd: nand_mrvl_nfc: Add support for 4bit BCH HW ECC

Add support for 4bit HW ECC modes supported by later IP versions. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Cc: Ezequiel Garcia <ezequ...

[PATCH 10/17] mtd: nand_mrvl_nfc: Prepare for different HW ECC strengths

Newer versions of Marvell PXA3xx NFC also support BCH and therefore higher ECC strengths than 1. Prepare for different ECC strength by factoring out ECC init into separate functions by strength. Also, add a new host variable that indicates BCH ECC. Signed-off-by: Sebastian Hesselbarth

[PATCH 17/17] mtd: nand_mrvl_nfc: Add optimized timings for Samsung K9K8G08U

This adds optimized timings for Samsung K9K8G08U 1Gb NAND flash. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Cc: Ezequiel Garcia <ezequ...@van

[PATCH 07/17] mtd: nand_mrvl_nfc: Use Auto Read Status on program/erase

Marvell NAND controller allows to enable an Auto Read Status feature that will monitor NAND status during Erase and Program operations. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni &l

[PATCH 14/17] mtd: nand_mrvl_nfc: Add support for HW BCH ECC

Add support for HW BCH ECC for those HW versions that support it. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> --- Cc: Robert Jarzmik <robert.jarz...@free.fr> Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com> Cc: Ezequiel Garcia <ezequ...

Re: [PATCH 01/13] net: phy: Support Marvell 88E1318S PHY

On 03.05.2015 11:50, Sebastian Hesselbarth wrote: On 02.05.2015 22:28, Ezequiel Garcia wrote: On 05/02/2015 01:53 PM, Ezequiel Garcia wrote: On 04/09/2015 10:03 PM, Sebastian Hesselbarth wrote: This adds support for the Marvell 88E1318S Gigabit Ethernet PHY. Signed-off-by: Sebastian

Re: [PATCH 01/13] net: phy: Support Marvell 88E1318S PHY

On 02.05.2015 22:28, Ezequiel Garcia wrote: On 05/02/2015 01:53 PM, Ezequiel Garcia wrote: On 04/09/2015 10:03 PM, Sebastian Hesselbarth wrote: This adds support for the Marvell 88E1318S Gigabit Ethernet PHY. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com

[PATCH v2 11/14] ARM: mvebu: armada-xp: Use MBUS_ERR_PROP_EN define

With proper defines for ARMADA_370_XP_FABRIC_CTRL and MBUS_ERR_PROP_EN make use of it. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free

[PATCH v2 13/14] ARM: mvebu: armada-xp: Add Lenovo Iomega ix4-300d

This adds support for Marvell Armada XP based 4-bay NAS Lenovo Iomega ix4-300d. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com

[PATCH v2 05/14] bus: mvebu-mbus: Remove coherency attribute

Marvell Armada 370 and XP have some coherency fabric. We are not interested in using it, so remove checking for it in mbus driver. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc

[PATCH v2 00/14] Add support for Lenovo ix4-300d NAS

/lists/u-boot-v2/msg23048.html Sebastian Hesselbarth (14): net: phy: Support Marvell 88E1318S PHY gpio: Add driver for 74x164 compatible shift-registers spi: ath79: move spidelay from spi-bitbang-txrx spi: Add SPI GPIO bitbang driver bus: mvebu-mbus: Remove coherency attribute bus: mvebu

[PATCH v2 12/14] ARM: mvebu: armada-xp: Sort boards and images alphabetically

Before adding new Armada XP based boards becomes messier than necessary, sort Armada XP based board Kconfig and image Makefile alphabetically. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free

[PATCH v2 07/14] bus: mvebu-mbus: Convert mbus platform driver to direct driver

Registering mbus driver as platform driver is a little late for some register accesses to work. We have to make sure boot-up mbus windows are disabled early, so call mbus driver directly from SoC init. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox

[PATCH v2 01/14] net: phy: Support Marvell 88E1318S PHY

This adds support for the Marvell 88E1318S Gigabit Ethernet PHY. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com --- drivers

[PATCH v2 09/14] ARM: mvebu: armada-xp: Fixup broken MV78230-A0 SoC ID

Marvell Armada XP MV78230-A0 incorrectly identifies itself as MV78460. Check number of CPUs in FABRIC_CONF and fixup PCIe DEV_ID when it is 2 CPUs instead of 4. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia

[PATCH v2 02/14] gpio: Add driver for 74x164 compatible shift-registers

A 74x164 shift register can be seen as a SPI attached GPIO expander. This adds a driver for those poor-man expanders based on the Linux driver. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free

[PATCH v2 08/14] ARM: mvebu: Move PCIe register defines to socid.h

To prepare PCIe device id fixups, move PCIe register defines to a common location. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free

[PATCH v2 03/14] spi: ath79: move spidelay from spi-bitbang-txrx

Bitbang helpers for SPI require spidelay. This should be set by the user and not the helper itself. Move it to ath79_spi instead. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc

[PATCH v2 06/14] bus: mvebu-mbus: Drop device reference

Prior converting mbus driver from a platform device back to directly called SoC driver, drop the device_d reference and covert dev_foo to pr_foo. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free

[PATCH v2 04/14] spi: Add SPI GPIO bitbang driver

This adds a driver for SPI master by GPIO pins. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com --- drivers/spi/Kconfig

[PATCH v2 10/14] ARM: mvebu: armada-xp: Limit PUP access to Armada XP

register defines to SYSCTL registers where they belong to. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free-electrons.com --- arch/arm/mach

[PATCH v2 14/14] ARM: Add Lenovo ix4 and related drivers to mvebu_defconfig

Update mvebu_defconfig to cover recently introduced Lenovo ix4 and its related drivers. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: barebox@lists.infradead.org Cc: Ezequiel Garcia ezequiel.gar...@free-electrons.com Cc: Thomas Petazzoni thomas.petazz...@free

Re: [PATCH 00/13] Add support for Lenovo ix4-300d NAS

On 04/14/2015 10:43 AM, Sascha Hauer wrote: This series looks ok to me. Does it make sense to apply it without the deferred probing patches or should I better wait for it? Sascha, please wait for the reworked deferred probing series. While reworking it, I also converted gpio-orion from

Re: [PATCH v2] USB: xHCI: Sync non-coherent DMA buffers

On 14.04.2015 20:52, Sascha Hauer wrote: On Mon, Apr 13, 2015 at 04:22:30PM +0200, Sebastian Hesselbarth wrote: --- Changelog: v1-v2: - balance dma_sync_single_foo() calls (Reported by Lucas Stach) Cc: barebox@lists.infradead.org Cc: Lucas Stach d...@lynxeye.de Seems your git send-email

[PATCH v2 4/6] led: gpio: Properly deal with deferred probing

-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2: - Drop static registered bitmap as two gpio-leds nodes will both call led_gpio_of_probe(). The second call will find the static variable modified and skip some leds. - Use a pre-allocated array of struct gpio_led

[PATCH v2 1/6] base: Introduce deferred probing

As expected, we would need deferred probing sooner or later. This is a first approach to allow devices to return -EPROBE_DEFER and get sorted into a list of deferred devices that will be re-probed later. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2

[PATCH v2 5/6] led: gpio: Free GPIOs on unregister()

Free requested GPIOs on unregistration of mono-, bi-, and tri-color GPIO leds. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2: - new patch Cc: barebox@lists.infradead.org --- drivers/led/led-gpio.c | 6 ++ 1 file changed, 6 insertions(+) diff

[PATCH v2 2/6] gpio: Return -EPROBE_DEFER on gpio_get_num()

GPIO drivers can be registered quite late in registration process causing dependant devices to fail probing. If we know gpio_get_num will be called with a non-NULL device, return -EPROBE_DEFER instead of -ENODEV to allow re-probing later. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba

[PATCH v2 0/6] Introduce deferred probing

could use some support -EPROBE_DEFER but IMHO we should wait for someone to actually force probe deferral there. Sebastian Hesselbarth (6): base: Introduce deferred probing gpio: Return -EPROBE_DEFER on gpio_get_num() OF: gpio: Silence error message on -EPROBE_DEFER led: gpio: Properly deal

[PATCH v2 3/6] OF: gpio: Silence error message on -EPROBE_DEFER

With deferred probing, -EPROBE_DEFER is not worth spilling an error. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2: - Also return early on gpio_get_num() == -EPROBE_DEFER Cc: barebox@lists.infradead.org --- drivers/of/of_gpio.c | 8 +--- 1 file

[PATCH v2 6/6] gpio: orion: Convert to platform_driver

With support for deferred probing, we can now relax driver registration for Marvell Orion GPIO driver from postcore_initcall() to normal platform_driver. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2: - new patch Cc: barebox@lists.infradead.org

[PATCH v2] USB: xHCI: Sync non-coherent DMA buffers

When working with non-coherent transfer buffers, we have to sync device and cpu for outgoing and incoming buffers. Fix the driver where non-coherent buffers are used in device context. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2: - balance

Re: [PATCH 1/4] base: Introduce deferred probing

On 13.04.2015 08:54, Sascha Hauer wrote: On Fri, Apr 10, 2015 at 03:02:43AM +0200, Sebastian Hesselbarth wrote: As expected, we would need deferred probing sooner or later. This is a first approach to allow devices to return -EPROBE_DEFER and get sorted into a list of deferred devices

Re: [RFC 2/2] mci: add Marvell Dove SDHCI driver

On 18.02.2015 00:43, Michael Grzeschik wrote: On Fri, Jul 05, 2013 at 11:22:19PM +0200, Sebastian Hesselbarth wrote: Nice! It just bumped up the RFC from 1.5yrs back to top in my barebox mail folder ;) This adds a driver for the SDHCI controller found on Marvell Dove SoCs. Despite a missing

Re: [PATCH RFT 17/24] net: orion-gbe: convert to streaming DMA ops

On 12.02.2015 22:39, Lucas Stach wrote: Lucas, I really enjoy reading commit logs, but I cannot find any on this one. ;) Mind adding a few words for the final patch set? I'll give it a go on Dove and Kirkwood in the next few days, but be aware that there is still no cache support on both

Re: [PATCH v3 0/4] mvebu: Add network support for Armada 370/XP

On 11/13/2014 10:09 AM, Uwe Kleine-König wrote: On Wed, Nov 12, 2014 at 12:22:22PM +0100, Sebastian Hesselbarth wrote: On 11/12/2014 11:56 AM, Uwe Kleine-König wrote: Hello again, here come the recent insights. [...] It seems to be not possible to easily dump the register space in both U

Re: [PATCH v3 0/4] mvebu: Add network support for Armada 370/XP

On 11/13/2014 11:46 AM, Uwe Kleine-König wrote: On Thu, Nov 13, 2014 at 10:53:46AM +0100, Sebastian Hesselbarth wrote: On 11/13/2014 10:09 AM, Uwe Kleine-König wrote: On Wed, Nov 12, 2014 at 12:22:22PM +0100, Sebastian Hesselbarth wrote: On 11/12/2014 11:56 AM, Uwe Kleine-König wrote: Hello

Re: [PATCH v3 0/4] mvebu: Add network support for Armada 370/XP

On 11/10/2014 07:43 PM, Uwe Kleine-König wrote: On Mon, Nov 10, 2014 at 03:10:56PM -0300, Ezequiel Garcia wrote: On 11/10/2014 05:06 AM, Uwe Kleine-König wrote: I tested this series on top of 784b352aeeed with a patch to support my ReadyNAS 104 (by Netgear, Armada 370 system, currently only

Re: [PATCH v2 6/6] ARM: Add mvebu_defconfig

On 09/17/2014 10:22 PM, Sebastian Hesselbarth wrote: From: Sascha Hauer s.ha...@pengutronix.de This adds a mvebu_defconfig which enables all mvebu based boards. Signed-off-by: Sascha Hauer s.ha...@pengutronix.de Acked-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com

Re: [PATCH v2 0/6] mvebu multi SoC support

On 09/19/2014 07:47 AM, Sascha Hauer wrote: On Wed, Sep 17, 2014 at 10:22:38PM +0200, Sebastian Hesselbarth wrote: This is v2 of the Multi-SoC series for MVEBU. It has been tested on Kirkwood (Guruplug), Dove (CuBox), and Armada 370 (Mirabox) with the very same non-EABI binary. It should also

Re: [PATCH v2 0/6] mvebu multi SoC support

On 09/19/2014 09:55 AM, Sascha Hauer wrote: On Fri, Sep 19, 2014 at 08:44:09AM +0200, Sebastian Hesselbarth wrote: On 09/19/2014 07:47 AM, Sascha Hauer wrote: On Wed, Sep 17, 2014 at 10:22:38PM +0200, Sebastian Hesselbarth wrote: This is v2 of the Multi-SoC series for MVEBU. It has been

Re: [PATCH 2/5] ARM: mvebu: Simplify memory init order

On 09/17/2014 08:45 AM, Sascha Hauer wrote: On Tue, Sep 16, 2014 at 10:05:44PM +0200, Sebastian Hesselbarth wrote: On 09/15/2014 09:41 AM, Sascha Hauer wrote: The initialisation of the memory nodes on mvebu is a bit compilcated: pure_initcall(mvebu_memory_fixup_register

[PATCH v2 4/6] ARM: mvebu: Check for correct SoC in of_fixup callback

From: Sascha Hauer s.ha...@pengutronix.de Only run the fixup when we are actually on the corresponding SoC. Signed-off-by: Sascha Hauer s.ha...@pengutronix.de Acked-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Cc: Sascha Hauer s.ha...@pengutronix.de Cc: Ezequiel Garcia

[PATCH v2 5/6] ARM: mvebu: Allow multiple SoCs

From: Sascha Hauer s.ha...@pengutronix.de Now that the correct SoC specific memory fixup function is called we can allow to select multiple SoCs in Kconfig. Signed-off-by: Sascha Hauer s.ha...@pengutronix.de Acked-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2

[PATCH v2 1/6] ARM: mvebu: Add common reset_cpu function

From: Sascha Hauer s.ha...@pengutronix.de mvebu has a reset_cpu function per SoC this does not work when multiple SoCs are selected, so add a common reset_cpu function which calls into the SoC specific ones. Signed-off-by: Sascha Hauer s.ha...@pengutronix.de Acked-by: Sebastian Hesselbarth

[PATCH v2 3/6] ARM: mvebu: Simplify memory init order

() kirkwood_init_soc() mvebu_set_memory(phys_base, phys_size); Signed-off-by: Sascha Hauer s.ha...@pengutronix.de Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Changelog: v1-v2: - remove pure_initcall(mvebu_memory_fixup_register) here - also move

[PATCH v2 2/6] ARM: mvebu: Add machine compatible to mbus ranges

Multi-SoC support for MVEBU will add mbus ranges for all compiled SoCs. To protect the mbus node of the SoC barebox is executed on from others ranges, pass machine's compatible to mvebu_mbus_add_range and check before applying the fixup. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba

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