Ooops I forgotten. I'm pretty sure the Matlab to implement FOC is already a
possibility on Cortex R4 that's never going to happen for PRU
Vector control, also called field-oriented control (FOC), is a
variable-frequency drive (VFD) control method in which the stator currents of a
three-phase AC
Even Nick the TI resident PRU genius used 2 PRU to implement his FOC reference
design.The AM64 demo app uses one Cortex ARM R4 to do the same thing. On a SOC
like AM64x the PRU would only be needed if you ran out of peripherals.Amazing
demo one R4 is running FFT no need to pass anything back to
Slightly off subject but to me this AM64 looks big
https://training.ti.com/sitara-am64x-processors-combine-powerful-communication-and-real-time-performance
1Meg of SRAM split between the 4 Cortex R4 that can run bare metal or Free RTOS
and in next release instead of waiting for Linux to boot to
Both PRUs exchange the last ring buffer writing position by DRam (or scratch
pad).
Too many RAMS we need to be clear to avoid confusion please
DDR is DRAM
Internal RAM is SRAM and there are several
SBL ARM internal SRAM (fast from ARM)PRU shared RAMPRU data and instruction
RAM( fastest for PRU)Th
I don't understand that concept. When you switch bits in the STEPENABLE
register, you'd loose accurate ADC timing. What sampling rate are you
talking about?
AFAIR your target is to controlling two eletromagnetic valves (water
medium?). They've a latency of more than 10 ms -> sampling rate &
co
Mark - I think I waited a day or maybe two. They've engaged and are
answering my questions. It's congruent with what is being shared here.
Walter
On Friday, June 11, 2021 at 5:28:54 PM UTC-4 lazarman wrote:
> Hello Walter
>
> Two ansychronous processor's it's entirely possible eventually ones
Good info. I'm going to set up some testing. Thank you!
On Monday, June 14, 2021 at 3:23:29 AM UTC-4 lazarman wrote:
> #The question is can PRU0 read FIFO0 while PRU1 #might try to read FIFO1
> at the same time?
>
> If these FIFOS are in Data RAM it's recommended to use shared memory.
> Wha
I am thinking that I'll have PRU0 do all the configuration and enabling of
the TSC and have the values for the two sensors that I want PRU1 to monitor
put in FIFO1. I'll have PRU0 only read from FIFO0 and let PRU1 only read
from FIFO1.
I will set up the three I want to read in one-shot mode a
#The question is can PRU0 read FIFO0 while PRU1 #might try to read FIFO1 at the
same time?
If these FIFOS are in Data RAM it's recommended to use shared memory. What's
confusing is as I understood it there's a PRU shared RAM and another larger
shared memory so sample code must be inspected care
wal...@edenconceptsllc.com schrieb am Freitag, 11. Juni 2021 um 18:44:27
UTC+2:
> ... setting up steps 1, 2 and 3 to read three analog lines in one-shot
> mode while steps 4 & are set up to read the other two analog lines in
> continous mode. I'll write data from steps 1, 2 and 3 into FIFO0 a
Hello Walter
Two ansychronous processor's it's entirely possible eventually ones writing and
other is reading and gets bad Data that's why they invented hardware dual port
ram.
Ping pong circular buffer's work on one processor systems you disable
interrupts in critical regions or lock it with a
I'm going to hold on to this as a backup option. I'm already using the
shared memory space so that's another option but writing to PRU0's local
RAM may be faster. I don't know. The monitor/control that PRU1 is doing
doesn't would be just fine with a 1-second read interval I think. The
thr
On Fri, 11 Jun 2021 09:44:27 -0700 (PDT), in
gmane.comp.hardware.beagleboard.user Walter Cromer
wrote:
>I can have PRU1 do all the ADC configuration including setting up steps 1,
>2 and 3 to read three analog lines in one-shot mode while steps 4 & are set
>up to read the other two analog lines
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