v variable OCL_OPTIMIZE_SEL_IR
Signed-off-by: Guo Yejun
---
backend/src/CMakeLists.txt | 1 +
backend/src/backend/gen_context.cpp| 3 +
backend/src/backend/gen_insn_selection.cpp | 1 +
backend/src/backend/gen_insn_selection.hpp | 5 ++
.../s
Please ignore this patch, I did some minor changes and will re-send together
with other patches.
-Original Message-
From: Guo, Yejun
Sent: Monday, August 31, 2015 8:41 AM
To: beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: [PATCH] add basic function to dump Selection IR
Selection
cate of code in
check_op1_extension()?", yes, it is a duplicate code, will be removed in v2.
For others, Chuanbo will refine and send out the v2 patch.
-Original Message-
From: Song, Ruiling
Sent: Sunday, September 06, 2015 3:02 PM
To: Weng, Chuanbo; beignet@lists.freedesktop.org
Cc: Guo,
Selection IR is a representation between Gen IR and Gen ASM, it is
almost a Gen instruction but *before* the register allocation.
only basic dump supported, not fully completed yet.
Signed-off-by: Guo Yejun
---
backend/src/CMakeLists.txt| 2 +
backend/src/backend
4 comments inline, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
xionghu@intel.com
Sent: Friday, August 28, 2015 3:52 PM
To: beignet@lists.freedesktop.org
Cc: Luo, Xionghu
Subject: [Beignet] [patch v2 2/3] enable create image 2d f
the earlier the instruction is generated, the more possible optimization
could be applied.
Signed-off-by: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 22 ++
backend/src/backend/gen_context.cpp| 46 +-
backend/src/backend
originally, the dst of simd_shuffle is not uniform, but if it is
optimized as scalar, just use simd_width=1 to generate sel_op/asm
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_insn_selection.cpp | 5 +
1 file changed, 5 insertions(+)
diff --git a/backend/src/backend
initialize the data inside kernel with packed integer vector
V2: call functions from ctx, instead of ctx.registerAllocator
Signed-off-by: Guo Yejun
---
backend/src/backend/context.cpp| 10 -
backend/src/backend/context.hpp| 2 +-
backend/src/backend
5:00 PM
To: Guo, Yejun; beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: RE: [Beignet] [PATCH] remove GBE_CURBE_STACK_POINTER in payload
Some comments.
> -Original Message-
> From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf
> Of Guo Yejun
> Sent:
LGTM, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
Manasi Navare
Sent: Tuesday, August 18, 2015 7:17 PM
To: beignet@lists.freedesktop.org
Cc: Navare, Manasi D
Subject: [Beignet] [PATCH 1/3] backend/src/backend: Handle
-dump-opt-llvm
the defines inside 'enum OpenFlags' changed from llvm 3.4 to 3.5,
since we are creating a file for write, just use llvm::sys::fs::F_None
which is defined by both 3.4 and 3.5
also change the flag to F_None for llvm3.6, since the it is not necessary
to use F_RW.
Signed-off-by:
Hi Manasi,
Please refer to the patch I sent yesterday to handle LLVM 3.3. We'd use '0'
instead of ' llvm::sys::fs::F_RW' for LLVM3.3, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
Manasi Navare
Sent: Thursday, August 13, 2015 8:59 P
initialize the data inside kernel with packed integer vector
Signed-off-by: Guo Yejun
---
backend/src/backend/context.cpp| 66 ++
backend/src/backend/context.hpp| 61 ++-
backend/src/backend/gen75_context.cpp | 4
LGTM, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
Midhun Kodiyath
Sent: Monday, August 10, 2015 11:35 PM
To: beignet@lists.freedesktop.org
Cc: Kodiyath, Midhunchandra
Subject: [Beignet] [PATCH] Set proper Vendor ID
Device ID and ve
llvm 3.3 has a different constructure of llvm::raw_fd_ostream
V2: refine the code
Signed-off-by: Guo Yejun
---
backend/src/backend/program.cpp | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/backend/src/backend/program.cpp b/backend/src/backend/program.cpp
index
Sure, let me send v2 for this style.
-Original Message-
From: Song, Ruiling
Sent: Thursday, August 13, 2015 9:57 AM
To: Guo, Yejun; beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: RE: [Beignet] [PATCH] fix issue when build against llvm3.3
> -Original Message-
>
llvm 3.3 has a different constructure of llvm::raw_fd_ostream
Signed-off-by: Guo Yejun
---
backend/src/backend/program.cpp | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/backend/src/backend/program.cpp b/backend/src/backend/program.cpp
index 9caf1ac..5f4277a
get_sub_group_id ranges at [0, 7] for SIMD8 and [0, 15] for SIMD16,
previously we set up the values in kernel payload, now change it
to generate the values inside kernel with packed integer vector.
v2: encapsulate into a function so that others can get the lane id easily.
Signed-off-by: Guo Yejun
The sel.push()/pop() is already at the beginning/end of the function, shall I
add it again?
Btw, I plan to encapsulate into a function so that others can get the lane id
easily.
-Original Message-
From: Yang, Rong R
Sent: Monday, August 10, 2015 11:37 AM
To: Guo, Yejun; beignet
get_sub_group_id ranges at [0, 7] for SIMD8 and [0, 15] for SIMD16,
previously we set up the values in kernel payload, now change it
to generate the values inside kernel with packed integer vector.
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_context.cpp| 8
backend
Yes, thanks.
-Original Message-
From: Song, Ruiling
Sent: Thursday, August 06, 2015 11:00 AM
To: Guo, Yejun; beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: RE: [Beignet] [PATCH] do not force float for immediate value load
The patch LGTM. But I think below description is a little
float format is used to load immediate value with TYPE_U32/TYPE_S32,
actually it is not necessary since it is not a performance sensitive
point.
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_insn_selection.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a
Got it, thanks.
The ASM is outputted for human reading, it is expected that a correct and human
readable format is used.
-Original Message-
From: Song, Ruiling
Sent: Tuesday, August 04, 2015 12:41 PM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: [Beignet] [PATCH] output
Yes, it would be better, not sure why the current code generates "F" for the
mov instruction, I'll take a look.
-Original Message-
From: Song, Ruiling
Sent: Tuesday, August 04, 2015 10:45 AM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: [Beignet] [PATC
value). And, to get the exact value
of aaa (with real format uint), the hex format is a necessary.
-Original Message-
From: Song, Ruiling
Sent: Friday, July 31, 2015 4:02 PM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: [Beignet] [PATCH] output float immediate value with %f i
Ping for review, thanks.
-Original Message-
From: Guo, Yejun
Sent: Thursday, July 23, 2015 8:48 AM
To: beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: [PATCH] output float immediate value with %f instead of %g
In disassemble, a float immediate value is printf with %g, it outputs a
In disassemble, a float immediate value is printf with %g, it
outputs a wrong value with 8 bytes, change it to be %f with the
correct 4 bytes. At some cases, the real data type is not float,
so also print the value in hex format.
Signed-off-by: Guo Yejun
---
backend/src/backend/gen
SimdShuffleInstruction::wellFormed
set dag.child[0]->root = 1
Signed-off-by: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 38 ++--
backend/src/backend/gen8_context.hpp | 1 +
backend/src/backend/gen_context.cpp|
: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 38 ++--
backend/src/backend/gen8_context.hpp | 1 +
backend/src/backend/gen_context.cpp| 68 --
backend/src/backend/gen_context.hpp| 1 +
.../src
the binary pattern assumes the two src operands have the same type,
while simd shuffle is not the case, so add a separate pattern for it.
Signed-off-by: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 38 ++--
backend/src/backend/gen8_context.hpp | 1
the regression is caused when only enable CL_UNORM_INT8 for CL_RG,
the reason is that during the image copy implementation with internal
kernel, all formats are considerd as integer format, it becomes
unknown since CL_UNSIGNED_INT8 is not enabled yet.
Signed-off-by: Guo Yejun
---
src/cl_image.c
Signed-off-by: Guo Yejun
---
src/cl_image.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/cl_image.c b/src/cl_image.c
index 9907f90..3a4be82 100644
--- a/src/cl_image.c
+++ b/src/cl_image.c
@@ -134,6 +134,11 @@ cl_image_get_intel_format(const cl_image_format *fmt)
case
Ping for review, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Guo
Yejun
Sent: Monday, May 04, 2015 4:47 PM
To: beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: [Beignet] [PATCH] correct the src output of alu3 when
v2: correct kernel to be suitable for simd_width both 8 and 16
Signed-off-by: Guo Yejun
---
kernels/compiler_sub_group_shuffle.cl | 18 ++
utests/compiler_sub_group_shuffle.cpp | 45 +++
2 files changed, 63 insertions(+)
create mode 100644 kernels
it is defined in
https://www.khronos.org/registry/cl/extensions/intel/cl_intel_subgroups.txt
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_insn_selection.cpp | 2 ++
backend/src/libocl/include/ocl_misc.h | 8 --
backend/src/libocl/tmpl/ocl_simd.tmpl.h| 2 ++
backend/src
Signed-off-by: Guo Yejun
---
kernels/compiler_sub_group_shuffle.cl | 18 ++
utests/compiler_sub_group_shuffle.cpp | 45 +++
2 files changed, 63 insertions(+)
create mode 100644 kernels/compiler_sub_group_shuffle.cl
create mode 100644 utests
Please ignore this patch set, I'll send a new patch set, thanks.
-Original Message-
From: Guo, Yejun
Sent: Tuesday, May 12, 2015 1:34 PM
To: beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: [PATCH 2/2] add utest for intel_sub_group_shuffle
Signed-off-by: Guo Yejun
---
ke
-off-by: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 23 ++---
backend/src/backend/gen_context.cpp| 32 ++
backend/src/backend/gen_insn_selection.cpp | 12 +++
backend/src/backend/gen_insn_selection.hxx | 1 +
backend/src
Signed-off-by: Guo Yejun
---
backend/src/libocl/tmpl/ocl_simd.tmpl.h| 8 ++--
backend/src/llvm/llvm_gen_ocl_function.hxx | 5 +++--
kernels/compiler_get_simd_id.cl| 8
kernels/compiler_get_simd_size.cl | 5 -
kernels/compiler_get_sub_group_id.cl
Signed-off-by: Guo Yejun
---
kernels/compiler_sub_group_shuffle.cl | 15
utests/CMakeLists.txt | 3 ++-
utests/compiler_sub_group_shuffle.cpp | 44 +++
3 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644 kernels
-off-by: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 23 ++---
backend/src/backend/gen_context.cpp| 32 ++
backend/src/backend/gen_insn_selection.cpp | 12 +++
backend/src/backend/gen_insn_selection.hxx | 1 +
backend/src
, 2015 8:01 AM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re: [Beignet] [PATCH] add introduction to build Beignet with yocto
Yejun thanks for the patch. It looks good, but it's better to get some one help
to test this method on Yocto.
On Mon, May 11, 2015 at 01:53:49PM +0800
Signed-off-by: Guo Yejun
---
docs/Beignet.mdwn| 2 +-
docs/howto/cross-compiler-howto.mdwn | 75 ++--
2 files changed, 73 insertions(+), 4 deletions(-)
diff --git a/docs/Beignet.mdwn b/docs/Beignet.mdwn
index 90a00e5..ec528b5 100644
--- a
It is a message from libdrm, what’s your exact version of libdrm and linux
kernel?
I did not see this message at my Ubuntu14.04 64bit system with libdrm 2.4.58
(built from source) and linux kernel 3.19 (download from kernel.org)
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Be
point inside
beignet (built with Debug version)
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Gao,
Sanshan
Sent: Monday, May 04, 2015 6:05 PM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re: [Beignet] Shared Host Memory but not Share
Thanks for your
Signed-off-by: Guo Yejun
---
backend/src/backend/gen/gen_mesa_disasm.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/backend/src/backend/gen/gen_mesa_disasm.c
b/backend/src/backend/gen/gen_mesa_disasm.c
index f8d89e0..705f5e2 100644
--- a/backend/src
Please refer to the sample code in utests/runtime_use_host_ptr_buffer.cpp and
kernels/runtime_use_host_ptr_buffer.cl
To avoid internal copy, it requires libdrm version >= 2.4.58 and linux kernel
version >= 3.16
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of Gao,
San
Signed-off-by: Guo Yejun
---
kernels/compiler_simd_shuffle.cl | 15 ++
utests/CMakeLists.txt| 3 ++-
utests/compiler_simd_shuffle.cpp | 44
3 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644 kernels
-by: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 23 ++---
backend/src/backend/gen_context.cpp| 32 ++
backend/src/backend/gen_insn_selection.cpp | 12 +++
backend/src/backend/gen_insn_selection.hxx | 1 +
backend/src/ir
Signed-off-by: Guo Yejun
---
kernels/compiler_get_simd_id.cl | 8
utests/CMakeLists.txt | 3 ++-
utests/compiler_get_simd_id.cpp | 33 +
3 files changed, 43 insertions(+), 1 deletion(-)
create mode 100644 kernels/compiler_get_simd_id.cl
uint __gen_ocl_get_simd_id();
return value ranges from 0 to simdsize - 1
V2: use function sel.selReg to refine code
V3: correct the uniform condition in liveness.cpp
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_context.cpp| 9 -
backend/src/backend/gen_insn_selection.cpp
Please ignore this patch set because just found a performance issue caused by
the change in liveness.cpp
-Original Message-
From: Guo, Yejun
Sent: Monday, April 20, 2015 9:28 AM
To: Yang, Rong R; beignet@lists.freedesktop.org
Subject: RE: [Beignet] [PATCH V2 1/2] add simd level
-Original Message-
From: Yang, Rong R
Sent: Friday, April 17, 2015 5:12 PM
To: Guo, Yejun; beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: RE: [Beignet] [PATCH V2 1/2] add simd level function
__gen_ocl_get_simd_id
> -Original Message-
> From: Beignet [mailto:b
uint __gen_ocl_get_simd_id();
return value ranges from 0 to simdsize - 1
V2: use function sel.selReg to refine code
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_context.cpp| 9 -
backend/src/backend/gen_insn_selection.cpp | 6 ++
backend/src/backend/program.h
Signed-off-by: Guo Yejun
---
kernels/compiler_get_simd_id.cl | 8
utests/CMakeLists.txt | 3 ++-
utests/compiler_get_simd_id.cpp | 33 +
3 files changed, 43 insertions(+), 1 deletion(-)
create mode 100644 kernels/compiler_get_simd_id.cl
uint __gen_ocl_get_simd_id();
return value ranges from 0 to simdsize - 1
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_context.cpp| 9 -
backend/src/backend/gen_insn_selection.cpp | 8
backend/src/backend/program.h | 1 +
backend/src/ir
uint __gen_ocl_get_simd_size();
returns 8 if SIMD8, returns 16 if SIMD16
V2: add missing files
remove some unnecessary functions
V3: correct the dst register setting, it is possible not uniform
V4: remove unnecessary function
Signed-off-by: Guo Yejun
---
backend/src/backend
Yes, thanks, will send out a new version
-Original Message-
From: Yang, Rong R
Sent: Thursday, April 16, 2015 10:34 AM
To: Guo, Yejun; beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: RE: [Beignet] [PATCH V3 1/2] add simd level function
__gen_ocl_get_simd_size
+void ALU0
Signed-off-by: Guo Yejun
---
kernels/compiler_get_simd_size.cl | 5 +
utests/CMakeLists.txt | 3 ++-
utests/compiler_get_simd_size.cpp | 32
3 files changed, 39 insertions(+), 1 deletion(-)
create mode 100644 kernels/compiler_get_simd_size.cl
uint __gen_ocl_get_simd_size();
returns 8 if SIMD8, returns 16 if SIMD16
V2: add missing files
remove unnecessary function
V3: correct the dst register setting, it is possible not uniform
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_insn_selection.cpp | 35
Signed-off-by: Guo Yejun
---
kernels/compiler_get_simd_size.cl | 5 +
utests/CMakeLists.txt | 3 ++-
utests/compiler_get_simd_size.cpp | 32
3 files changed, 39 insertions(+), 1 deletion(-)
create mode 100644 kernels/compiler_get_simd_size.cl
uint __gen_ocl_get_simd_size();
returns 8 if SIMD8, returns 16 if SIMD16
V2: add missing files
remove unnecessary function
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_insn_selection.cpp | 36 ++
backend/src/ir/context.hpp | 6
Please ignore this patch set since I missed to add another file.
-Original Message-
From: Guo, Yejun
Sent: Tuesday, April 14, 2015 4:07 PM
To: beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: [PATCH 1/2] add simd level function __gen_ocl_get_simd_size
uint __gen_ocl_get_simd_size
Signed-off-by: Guo Yejun
---
kernels/compiler_get_simd_size.cl | 5 +
utests/CMakeLists.txt | 3 ++-
utests/compiler_get_simd_size.cpp | 32
3 files changed, 39 insertions(+), 1 deletion(-)
create mode 100644 kernels/compiler_get_simd_size.cl
uint __gen_ocl_get_simd_size();
returns 8 if SIMD8, returns 16 if SIMD16
Signed-off-by: Guo Yejun
---
backend/src/backend/gen_insn_selection.cpp | 41 ++
backend/src/ir/context.hpp | 6 +
backend/src/ir/instruction.cpp | 30
LGTM, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
Zhigang Gong
Sent: Tuesday, April 14, 2015 1:47 PM
To: beignet@lists.freedesktop.org
Cc: Gong, Zhigang
Subject: [Beignet] [PATCH] GBE: should initialize useDWLabel to false by
defau
after this big
patch is accepted in the code.
-Original Message-
From: Yang, Rong R
Sent: Friday, April 03, 2015 1:47 PM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: [PATCH 1/2] add 3 simd level built-in functions: shuffle, simdsize
and simdid
Some comments.
Thank
Ask for review, thanks.
yejun
-Original Message-
From: Guo, Yejun
Sent: Friday, March 20, 2015 1:58 PM
To: beignet@lists.freedesktop.org
Cc: Guo, Yejun
Subject: [PATCH 1/2] add 3 simd level built-in functions: shuffle, simdsize and
simdid
uint __gen_ocl_get_simd_size();
returns 8 if
Signed-off-by: Guo Yejun
---
kernels/compiler_simd_shuffle.cl | 15 ++
utests/CMakeLists.txt| 1 +
utests/compiler_simd_shuffle.cpp | 44
3 files changed, 60 insertions(+)
create mode 100644 kernels/compiler_simd_shuffle.cl
value of x of the c-th channel of the SIMD is returned, for all SIMD
channels,
the behavior is undefined if c is larger than simdsize - 1
Signed-off-by: Guo Yejun
---
backend/src/backend/gen8_context.cpp | 29 -
backend/src/backend/gen_context.cpp| 127
Signed-off-by: Guo Yejun
---
docs/Beignet/Backend.mdwn | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/docs/Beignet/Backend.mdwn b/docs/Beignet/Backend.mdwn
index e4259fb..cf80318 100644
--- a/docs/Beignet/Backend.mdwn
+++ b/docs/Beignet/Backend.mdwn
@@ -48,10 +48,12
LGTM, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
xionghu@intel.com
Sent: Tuesday, March 17, 2015 1:26 PM
To: beignet@lists.freedesktop.org
Cc: Luo, Xionghu
Subject: [Beignet] [patch v2] strip PointerCast for call instructions b
Nice catch, LGTM, thanks.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
Zhigang Gong
Sent: Friday, February 06, 2015 5:53 PM
To: beignet@lists.freedesktop.org
Cc: Gong, Zhigang
Subject: [Beignet] [PATCH] runtime: don't free the host_ptr for a
The patch LGTM, thanks.
From: Weng, Chuanbo
Sent: Monday, February 02, 2015 3:06 PM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: version 4 of libva buffer sharing patchset
Removed and updated the patchset.
From: Guo, Yejun
Sent: Monday, February 02, 2015 14:11
To: Weng, Chuanbo
Looks fine except one comment: OUTPUT_NV12_DEFAULT is not really used, we can
just remove it.
From: Weng, Chuanbo
Sent: Thursday, January 29, 2015 11:33 AM
To: Guo, Yejun; beignet@lists.freedesktop.org
Subject: RE: version 4 of libva buffer sharing patchset
Hi Yejun,
Thanks for
Thanks Palmer for the investigation.
1. yes, the logic is not good to free an incompletely-set-up buffer, need to
fix it.
2. I currently have not reproduced the issue, and have no idea on the EINVAL
(errno=22).
Does the system run out of memory at that time?
Could you please help to add opti
how about
the test if the condition is not satisfied, maybe we need assert here.
From: Weng, Chuanbo
Sent: Friday, January 23, 2015 6:23 PM
To: beignet@lists.freedesktop.org; Guo, Yejun
Subject: version 4 of libva buffer sharing patchset
Hi all,
Please fetch the 4th version of patchset f
the limitation is loosed from page size to cache line size
alignment inside driver, update utest accordingly.
Signed-off-by: Guo Yejun
---
benchmark/benchmark_use_host_ptr_buffer.cpp | 2 +-
utests/runtime_use_host_ptr_buffer.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions
the current limitation is both host_ptr and buffer size should be
page aligned, loose the limitation of host_ptr to be cache line
size (64byte) alignment, and no limitation for the size.
Signed-off-by: Guo Yejun
---
src/cl_command_queue.c | 8 ++--
src/cl_mem.c | 17
the correct value of cache line size is 64 bytes, not 128.
Signed-off-by: Guo Yejun
---
src/cl_gen75_device.h | 2 +-
src/cl_gen7_device.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cl_gen75_device.h b/src/cl_gen75_device.h
index 8cf2dcd..43f6e8f 100644
--- a
, and build driver with it.
v3: add file FindStandaloneGbeCompiler.cmake to make the main cmakefile clean.
Signed-off-by: Guo Yejun
---
CMake/FindStandaloneGbeCompiler.cmake | 35 +++
CMakeLists.txt| 15 +++
GetGenID.sh
Signed-off-by: Guo Yejun
---
docs/howto/oldgcc-howto.mdwn | 58
1 file changed, 58 insertions(+)
create mode 100644 docs/howto/oldgcc-howto.mdwn
diff --git a/docs/howto/oldgcc-howto.mdwn b/docs/howto/oldgcc-howto.mdwn
new file mode 100644
index
the running system.
btw, please make sure compiler_ceil.bin is really updated if there is
already one there, the safe way is to delete it first.
Signed-off-by: Guo Yejun
---
CMakeLists.txt| 4
utests/CMakeLists.txt | 27 +++
2 files changed, 23 insertions
, and build driver with it.
Signed-off-by: Guo Yejun
---
CMakeLists.txt | 43 +++
GetGenID.sh| 26 ++
backend/CMakeLists.txt | 20 +---
backend/src/CMakeLists.txt | 20
: change the option name to BUILD_STANDALONE_GBE_COMPILER.
zip necessary files into a tar ball.
Signed-off-by: Guo Yejun
---
backend/src/CMakeLists.txt | 39 +--
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/backend/src/CMakeLists.txt b
libocl is the name of sub directory, the project name in the sub
directory, it is not something that others can depend on.
Signed-off-by: Guo Yejun
---
backend/src/CMakeLists.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/backend/src/CMakeLists.txt b/backend/src/CMakeLists.txt
index
Ok, it is also a practical method.
-Original Message-
From: Zhigang Gong [mailto:zhigang.g...@linux.intel.com]
Sent: Wednesday, January 07, 2015 12:56 PM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re: [Beignet] [PATCH 3/3] add CMAKE option ENABLE_RTTI for some stl
r 1
-Original Message-
From: Zhigang Gong [mailto:zhigang.g...@linux.intel.com]
Sent: Wednesday, January 07, 2015 12:13 PM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re: [Beignet] [PATCH 3/3] add CMAKE option ENABLE_RTTI for some stl
version
Can we just remove -fno-rtti? D
-t option specifies the gen target pci id, it tells gbe_bin_generater
the target platform that it compiles for. The compile result is llvm
level binary if this option is not given.
Signed-off-by: Guo Yejun
---
backend/src/gbe_bin_generater.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion
07, 2015 10:26 AM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re: [Beignet] [PATCH 3/3] add CMAKE option ENABLE_RTTI for some stl
version
Could you find out the specified STL version? And do some checking at
configuration time and remove or add fno-rtti according to the checking
Yes, I expected to compile with -t option. Will also refine the
gbe_bin_generator usage information.
-Original Message-
From: Zhigang Gong [mailto:zhigang.g...@linux.intel.com]
Sent: Wednesday, January 07, 2015 10:40 AM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re
ssage-
From: Zhigang Gong [mailto:zhigang.g...@linux.intel.com]
Sent: Wednesday, January 07, 2015 11:11 AM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: RE: [Beignet] [PATCH 2/3] support CL_EMBEDDED_PROFILE with offline
compiler
> -Original Message-
> From: Beignet
sable,
and the document, do not object your comments, and will modify accordingly.
-Original Message-
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
Zhigang Gong
Sent: Wednesday, January 07, 2015 8:31 AM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subjec
I’m afraid it is not in the plan, the expected method is to link with the
dynamic library libcl.so.
From: Beignet [mailto:beignet-boun...@lists.freedesktop.org] On Behalf Of
spring_wind
Sent: Wednesday, December 31, 2014 7:52 PM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re
: spring_wind [mailto:spring_w...@yeah.net]
Sent: Wednesday, December 31, 2014 4:30 PM
To: Guo, Yejun
Cc: beignet@lists.freedesktop.org
Subject: Re:[Beignet] [PATCH 1/3] add option BUILD_STATIC_GBE_COMPILER to build
static compiler
Do you have plan to support to build libcl and libgbe_interp in static
for some STL version, unable to build with -fno-rtti, have to enable it.
Signed-off-by: Guo Yejun
---
CMakeLists.txt | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5cb31c2..9b9c9ea 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
/your_path_to_compiler looks like:
beignet.bc beignet.pch gbe_bin_generater include
3. Within old environment, build with
STATIC_GBE_COMPILER_PATH=/your_path_to_compiler
libcl.so and libgbeinterp.so will be built here, libgbe.so and gbe_bin_generater
will not be built here.
Signed-off-by: Guo Yejun
The offline compiler (gbe_bin_generater), depending on LLVM/clang,
could only be built with C++11 features. To make it workable within
old c/c++ version environment, add one CMAKE option to link against
all static libraries.
Signed-off-by: Guo Yejun
---
backend/src/CMakeLists.txt | 33
change the keyword from constexpr to const, update the code for
explicit type conversion and std::map's iterator.
Signed-off-by: Guo Yejun
---
utests/compiler_displacement_map_element.cpp | 4 +--
utests/compiler_saturate.cpp | 2 +-
utests/compiler_saturate_su
OpenCL compiler)
which depends on LLVM/clang
Signed-off-by: Guo Yejun
---
backend/src/backend/program.cpp | 17 ---
backend/src/backend/program.hpp | 6 +--
backend/src/ir/constant.cpp | 3 +-
backend/src/ir/constant.hpp | 5 ++-
backend/src/ir/function.hpp | 22
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