[Bug ld/27180] RISC-V far relocations for auipc instructions may cause segfault with --emit-relocs

https://sourceware.org/bugzilla/show_bug.cgi?id=27180 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug ld/29823] ld riscv: undefined elf_backend_obj_attrs_handle_unknown causes segfault when merging .riscv.attributes

https://sourceware.org/bugzilla/show_bug.cgi?id=29823 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/31179] RISC-V: The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objects

https://sourceware.org/bugzilla/show_bug.cgi?id=31179 Nelson Chu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/31179] RISC-V: The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objects

https://sourceware.org/bugzilla/show_bug.cgi?id=31179 --- Comment #11 from Nelson Chu --- > So I think this is a roughly workable solution (maybe we should cache those > tag lookups for performance, not sure if it matters). It's going to be hard > to tell for sure without some distro testing,

[Bug ld/31179] RISC-V: The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objects

https://sourceware.org/bugzilla/show_bug.cgi?id=31179 --- Comment #8 from Nelson Chu --- Created attachment 15270 --> https://sourceware.org/bugzilla/attachment.cgi?id=15270=edit proposed solution with the tag to keep compatible Updated to have a tag, this patch should be applied after the

[Bug ld/31179] RISC-V: The SET/ADD/SUB fix breaks ABI compatibility with 2.41 objects

https://sourceware.org/bugzilla/show_bug.cgi?id=31179 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/30844] ld riscv: --emit-relocs does not retain the original relocation type

https://sourceware.org/bugzilla/show_bug.cgi?id=30844 --- Comment #4 from Nelson Chu --- > The --emit-relocs should switch to preserve the original > relocation type, including R_RISCV_CALL_PLT(etc), > R_RISCV_RELAX, and R_RISCV_ALIGN. Looks reasonable, so based on this rule when setting

[Bug ld/25694] R_RISCV_TPREL_HI20 relocations cause riscv64 to add TEXTREL bit on executables

https://sourceware.org/bugzilla/show_bug.cgi?id=25694 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug gas/30449] gas riscv: support pseudo-instruction "lga"

https://sourceware.org/bugzilla/show_bug.cgi?id=30449 Nelson Chu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug gas/30449] gas riscv: support pseudo-instruction "lga"

https://sourceware.org/bugzilla/show_bug.cgi?id=30449 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/24676] [RISCV] Redundant R_RISCV_DTPMOD* R_RISCV_DTPREL* resulted from Global Dynamic -> Local Exec relaxation

https://sourceware.org/bugzilla/show_bug.cgi?id=24676 --- Comment #5 from Nelson Chu --- Accidentally, this can also fix the redundant NOPs issue here, https://sourceware.org/pipermail/binutils/2023-May/127653.html -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/25694] R_RISCV_TPREL_HI20 relocations cause riscv64 to add TEXTREL bit on executables

https://sourceware.org/bugzilla/show_bug.cgi?id=25694 --- Comment #7 from Nelson Chu --- Thanks for the information, Andreas. There is a proposed solution as follows, which suggested by Alan, https://sourceware.org/pipermail/binutils/2023-May/127653.html The idea is that make sure using same

[Bug ld/27566] [RISC-V] relocation truncated to fit: R_RISCV_GPREL_I against aymbol

https://sourceware.org/bugzilla/show_bug.cgi?id=27566 Nelson Chu changed: What|Removed |Added Last reconfirmed||2023-05-10 Status|RESOLVED

[Bug ld/25694] R_RISCV_TPREL_HI20 relocations cause riscv64 to add TEXTREL bit on executables

https://sourceware.org/bugzilla/show_bug.cgi?id=25694 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/28789] RISC-V: ld resolves absolute symbols via PC-relative relocations for position-independent targets

https://sourceware.org/bugzilla/show_bug.cgi?id=28789 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/30282] risc-v: objdump is really slow

https://sourceware.org/bugzilla/show_bug.cgi?id=30282 Nelson Chu changed: What|Removed |Added Attachment #14785|0 |1 is patch|

[Bug binutils/30282] risc-v: objdump is really slow

https://sourceware.org/bugzilla/show_bug.cgi?id=30282 Nelson Chu changed: What|Removed |Added Summary|risc-v: objdump îs really |risc-v: objdump is really

[Bug binutils/30282] New: risc-v: objdump îs really slow

Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- Originally discussion, https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188 -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/30259] RISC-V: Assertion failed when trying to link from "code" section

https://sourceware.org/bugzilla/show_bug.cgi?id=30259 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/13302] IRELATIVE relocation should come last

https://sourceware.org/bugzilla/show_bug.cgi?id=13302 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/30099] objdump riscv: stop disassembling addi rd, rs, 0 with a relocation as mv rd, rs

https://sourceware.org/bugzilla/show_bug.cgi?id=30099 --- Comment #2 from Nelson Chu --- Some minor issues for implementation, * I like the idea from Maciej to define a new instruction type, INSN_NORELOC, in the opcode table. But seems like we didn't left enough encodings for INSN_TYPE, so the

[Bug binutils/30099] objdump riscv: stop disassembling addi rd, rs, 0 with a relocation as mv rd, rs

https://sourceware.org/bugzilla/show_bug.cgi?id=30099 --- Comment #1 from Nelson Chu --- Created attachment 14662 --> https://sourceware.org/bugzilla/attachment.cgi?id=14662=edit proposed solution v1 -- You are receiving this mail because: You are on the CC list for the bug.

[Bug binutils/30099] New: objdump riscv: stop disassembling addi rd, rs, 0 with a relocation as mv rd, rs

Severity: normal Priority: P2 Component: binutils Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- Copy from here, https://inbox.sourceware.org/binutils/ds7pr12mb57659139c1d9ea568403722dcb

[Bug ld/28509] ld riscv: R_RISCV_JAL referencing a preemptible symbol should be rejected

https://sourceware.org/bugzilla/show_bug.cgi?id=28509 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug gas/28863] two-argument .align is accepted for RISC-V but the alignment is not always preserved

https://sourceware.org/bugzilla/show_bug.cgi?id=28863 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/24683] RISC-V call and callplt reloc handling

https://sourceware.org/bugzilla/show_bug.cgi?id=24683 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/27809] RISC-V missing disassembler options in document

https://sourceware.org/bugzilla/show_bug.cgi?id=27809 Nelson Chu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/24226] Need advise on the binutils problem that generating wrong instruction like lw a3,-2048(a5) on RISC-V backend

https://sourceware.org/bugzilla/show_bug.cgi?id=24226 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/25501] STT_GNU_IFUNC causes assertion on 64-bit RISC-V

||nelsonc1225 at sourceware dot org Resolution|--- |FIXED --- Comment #10 from Nelson Chu --- This should be fixed since RISCV already supported IFUNC in gcc/binutils/glibc, so marked as RESOLVED and FIXED. We can re-open this or open a new one

[Bug ld/28509] ld riscv: R_RISCV_JAL referencing a preemptible symbol should be rejected

https://sourceware.org/bugzilla/show_bug.cgi?id=28509 --- Comment #2 from Nelson Chu --- It probably worth that back to see this one, I totally forgot it... https://sourceware.org/pipermail/binutils/2021-November/118398.html -- You are receiving this mail because: You are on the CC list for

[Bug gas/29004] various bugs in RISCV version of as

https://sourceware.org/bugzilla/show_bug.cgi?id=29004 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/29077] RISCV: .align directive interferes with relaxations

|--- |WONTFIX CC||nelsonc1225 at sourceware dot org --- Comment #2 from Nelson Chu --- We should reserve the maximum section alignment when doing relaxations, even if the section alignment doesn't seems to affect. Since sometimes

[Bug gas/29341] RISC-V: -march=rv32imcb fails due to cannot find default versions of the ISA extension `b'

https://sourceware.org/bugzilla/show_bug.cgi?id=29341 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/29342] RISC-V 32: disassembly mishandles negative symbols

||nelsonc1225 at sourceware dot org Resolution|--- |FIXED --- Comment #5 from Nelson Chu --- Marked as resolved and fixed since the following commit, commit 48525554d5222d98953202b9252ff65fdead58a4 Refs: gdb-12-branchpoint-1830-g48525554d52 Author

[Bug gas/28733] RISC-V: Bad errors on fence.i and CSR ISA checking

https://sourceware.org/bugzilla/show_bug.cgi?id=28733 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug gas/28793] [RISC-V] DW_cfa_advance_offset is not correct

https://sourceware.org/bugzilla/show_bug.cgi?id=28793 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug gas/28793] [RISC-V] DW_cfa_advance_offset is not correct

https://sourceware.org/bugzilla/show_bug.cgi?id=28793 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug gas/28733] RISC-V: Bad errors on fence.i and CSR ISA checking

https://sourceware.org/bugzilla/show_bug.cgi?id=28733 Nelson Chu changed: What|Removed |Added Assignee|unassigned at sourceware dot org |palmer at dabbelt dot com --

[Bug gas/28733] New: RISC-V: Bad errors on fence.i and CSR ISA checking

Component: gas Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- For now we just report the errors "unrecognized opcode" for the instruction which needs to enable some specific extensions. For example, nel

[Bug ld/28709] [RISC-V] a unused section can't be removed with -gc-sections

https://sourceware.org/bugzilla/show_bug.cgi?id=28709 --- Comment #5 from Nelson Chu --- (In reply to lifang_xia from comment #3) > The riscv backend will create a reloc named BFD_RELOC_RISCV_CFA in > riscv_pre_output_hook. The reloc depends on the symbol to(.L0) and > from(.L0). > > And riscv

[Bug ld/28709] [RISC-V] a unused section can't be removed with -gc-sections

https://sourceware.org/bugzilla/show_bug.cgi?id=28709 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/28684] New: [RISCV] 32-bit --enable-targets=all build breakage issue

Priority: P2 Component: binutils Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- The 32-bit build failed again when --enable-targets=all, the original discussion was here, https://sourceware.org/pipermail

[Bug gas/28610] ASAN error: in riscv_update_subset bfd/elfxx-riscv.c:2245

https://sourceware.org/bugzilla/show_bug.cgi?id=28610 Nelson Chu changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug gas/28610] ASAN error: in riscv_update_subset bfd/elfxx-riscv.c:2245

https://sourceware.org/bugzilla/show_bug.cgi?id=28610 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/28509] ld riscv: R_RISCV_JAL referencing a preemptible symbol should be rejected

CC||nelsonc1225 at sourceware dot org -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/28441] [RISCV] ld linker relaxation is really slow

https://sourceware.org/bugzilla/show_bug.cgi?id=28441 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/28410] Prevent region check failures when relaxation is not final

https://sourceware.org/bugzilla/show_bug.cgi?id=28410 Nelson Chu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/28410] Prevent region check failures when relaxation is not final

https://sourceware.org/bugzilla/show_bug.cgi?id=28410 --- Comment #7 from Nelson Chu --- > only restart the relax passes themselves. The purpose of `again` is used to rerun the relax passes themselves. That means once the `again` is always false for all input sections, and we decide to enter

[Bug ld/28410] Prevent region check failures when relaxation is not final

https://sourceware.org/bugzilla/show_bug.cgi?id=28410 --- Comment #5 from Nelson Chu --- Oh, sorry for the wrong description, we should update the tables in the _bfd_riscv_relax_section, rather than the tables in the riscv_elf_relocate_section. Otherwise, the idea should be similar. -- You

[Bug ld/28410] Prevent region check failures when relaxation is not final

https://sourceware.org/bugzilla/show_bug.cgi?id=28410 --- Comment #4 from Nelson Chu --- > I had thought about a possible approach to rewrite the commit, such that we > can restart the relaxation process again without modifying the `again` > pointer. Perhaps its worth me working on this if

[Bug ld/28410] Prevent region check failures when relaxation is not final

https://sourceware.org/bugzilla/show_bug.cgi?id=28410 --- Comment #2 from Nelson Chu --- commit abd20cb637008da9d32018b4b03973e119388a0a Refs: users/ARM/embedded-gdb-master-2018q4-7811-gabd20cb Author: Nelson Chu AuthorDate: Tue Nov 17 19:39:52 2020 -0800 Commit: Nelson Chu CommitDate:

[Bug ld/28410] Prevent region check failures when relaxation is not final

https://sourceware.org/bugzilla/show_bug.cgi?id=28410 --- Comment #1 from Nelson Chu --- Consider the testcase in the attached, nelson@LAPTOP-QFSGI1F2:~/test$ cat align.s .section .entry, "xa" .align 5 .globl _start .type _start, @function _start: tail _start .size _start, . - _start

[Bug ld/28410] New: Prevent region check failures when relaxation is not final

Priority: P2 Component: ld Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- Created attachment 13695 --> https://sourceware.org/bugzilla/attachment.cgi?id=13695=edit proposed solution from Lewis Rev

[Bug gas/28372] [RISCV] wrong attribute of version number generated for p extension

https://sourceware.org/bugzilla/show_bug.cgi?id=28372 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/27916] RISC-V: Porting ARM/AARCH64 mapping symbols to riscv.

https://sourceware.org/bugzilla/show_bug.cgi?id=27916 Nelson Chu changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug ld/24769] [RISCV] partial RELRO doesn't work: .got is not in PT_GNU_RELRO

https://sourceware.org/bugzilla/show_bug.cgi?id=24769 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/22756] Linker relaxation miscalculates symbol addresses on riscv

||nelsonc1225 at sourceware dot org Status|NEW |RESOLVED --- Comment #10 from Nelson Chu --- The pr28021 is related to this pr, and the new problem is resolved by Michael Matz. So also marked as resolved and fixed for pr22756. -- You

[Bug ld/27566] [RISC-V] relocation truncated to fit: R_RISCV_GPREL_I against aymbol

https://sourceware.org/bugzilla/show_bug.cgi?id=27566 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug ld/27953] IE->LE is not happening for riscv in linker relaxation.

https://sourceware.org/bugzilla/show_bug.cgi?id=27953 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/24676] [RISCV] Redundant R_RISCV_DTPMOD* R_RISCV_DTPREL* resulted from Global Dynamic -> Local Exec relaxation

https://sourceware.org/bugzilla/show_bug.cgi?id=24676 Nelson Chu changed: What|Removed |Added CC||chschandan at gmail dot com --- Comment

[Bug binutils/27916] RISC-V: Porting ARM/AARCH64 mapping symbols to riscv.

https://sourceware.org/bugzilla/show_bug.cgi?id=27916 Nelson Chu changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this

[Bug binutils/27916] RISC-V: Porting ARM/AARCH64 mapping symbols to riscv.

https://sourceware.org/bugzilla/show_bug.cgi?id=27916 Nelson Chu changed: What|Removed |Added Assignee|unassigned at sourceware dot org |nelsonc1225 at sourceware dot

[Bug binutils/27916] New: RISC-V: Porting ARM/AARCH64 mapping symbols to riscv.

Component: binutils Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- -- You are receiving this mail because: You are on the CC list for the bug.

[Bug gas/25212] [RISCV] gas doesn't flag invalid march and mabi combinations

https://sourceware.org/bugzilla/show_bug.cgi?id=25212 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/27814] objdump crashes when disassembling a non-ELF RISC-V binary

https://sourceware.org/bugzilla/show_bug.cgi?id=27814 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug binutils/27809] RISC-V missing disassembler options in document

https://sourceware.org/bugzilla/show_bug.cgi?id=27809 Nelson Chu changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this

[Bug binutils/27809] New: RISC-V missing disassembler options in document

Component: binutils Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- -Mnumeric and other dis-assembler options are missing in the binutils documents. -- You are receiving this mail because: You are on the CC list

[Bug ld/27180] RISC-V far relocations for auipc instructions may cause segfault with --emit-relocs

https://sourceware.org/bugzilla/show_bug.cgi?id=27180 --- Comment #2 from Nelson Chu --- Hi Julius, Thanks for reporting this. Your assumption is correct, the PCREL relocs are converted to the directly access relocs, but we don't update them to the relocation table, so we will get segment

[Bug ld/27180] RISC-V far relocations for auipc instructions may cause segfault with --emit-relocs

https://sourceware.org/bugzilla/show_bug.cgi?id=27180 Nelson Chu changed: What|Removed |Added Attachment #13402|application/mbox|text/plain mime type|

[Bug ld/27180] RISC-V far relocations for auipc instructions may cause segfault with --emit-relocs

https://sourceware.org/bugzilla/show_bug.cgi?id=27180 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/24676] [RISCV] Redundant R_RISCV_DTPMOD* R_RISCV_DTPREL* resulted from Global Dynamic -> Local Exec relaxation

https://sourceware.org/bugzilla/show_bug.cgi?id=24676 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/25258] RISC-V: relocation truncated to fit: R_RISCV_GPREL_I against `.LANCHOR2'

https://sourceware.org/bugzilla/show_bug.cgi?id=25258 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/25354] On RISCV64 LD, with EXACTLY 72 headers/sections, PhysAddr for first Program Header is wrong

||nelsonc1225 at sourceware dot org -- You are receiving this mail because: You are on the CC list for the bug.

[Bug gas/27215] as: Error: non-constant .uleb128 is not supported on riscv64

https://sourceware.org/bugzilla/show_bug.cgi?id=27215 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/27566] [RISC-V] relocation truncated to fit: R_RISCV_GPREL_I against aymbol

https://sourceware.org/bugzilla/show_bug.cgi?id=27566 Nelson Chu changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this

[Bug gas/27436] RISC-V inconsistent handling of rv32 shift with count > 31

||nelsonc1225 at sourceware dot org Status|NEW |RESOLVED --- Comment #3 from Nelson Chu --- Now I can have the expected results by using mainline binutils, nelson@LAPTOP-QFSGI1F2:~$ riscv32-unknown-elf-as -march=rv64g tmp.s nelson@LAPTOP-QFSGI1F2

[Bug gas/27732] RISC-V: Compress "addi a0, a1, 0" to "c.mv a0, a1"

https://sourceware.org/bugzilla/show_bug.cgi?id=27732 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug binutils/27584] nm riscv: Suppress empty name symbols unless --special-syms?

https://sourceware.org/bugzilla/show_bug.cgi?id=27584 --- Comment #7 from Nelson Chu --- $ cat tmp.s foo: lla a0, foo $ riscv64-unknown-elf-as tmp.s -o tmp-gnu.o $ riscv64-unknown-elf-nm tmp-gnu.o t foo riscv64-unknown-elf-nm --special-syms tmp-gnu.o

[Bug binutils/27585] addr2line riscv: Skip empty name symbols?

https://sourceware.org/bugzilla/show_bug.cgi?id=27585 --- Comment #1 from Nelson Chu --- The fixed in PR27584 doesn't affect the PR27585. The addr2line may be another problem and need to find another way to fix. -- You are receiving this mail because: You are on the CC list for the bug.

[Bug binutils/27584] nm riscv: Suppress empty name symbols unless --special-syms?

https://sourceware.org/bugzilla/show_bug.cgi?id=27584 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug gas/27732] RISC-V: Compress "addi a0, a1, 0" to "c.mv a0, a1"

https://sourceware.org/bugzilla/show_bug.cgi?id=27732 Nelson Chu changed: What|Removed |Added Summary|Compress "addi a0, a1, 0" |RISC-V: Compress "addi a0,

[Bug gas/27732] Compress "addi a0, a1, 0" to "c.mv a0, a1"

https://sourceware.org/bugzilla/show_bug.cgi?id=27732 Nelson Chu changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this

[Bug gas/27732] New: Compress "addi a0, a1, 0" to "c.mv a0, a1"

2 Component: gas Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- The idea comes from Lifang-Xia, and llvm already have the similar conversion, https://reviews.llvm.org/D45583 -- You are receiving th

[Bug binutils/27584] nm riscv: Suppress empty name symbols unless --special-syms?

https://sourceware.org/bugzilla/show_bug.cgi?id=27584 --- Comment #5 from Nelson Chu --- (In reply to Andreas Schwab from comment #4) > I think it would generally be useful to add an option to omit local .L > symbols from both nm and objdump output, including disassembler output. Thanks

[Bug ld/27566] [RISC-V] relocation truncated to fit: R_RISCV_GPREL_I against aymbol

https://sourceware.org/bugzilla/show_bug.cgi?id=27566 --- Comment #6 from Nelson Chu --- Jim's assumption is right, the gp won't overlap the rodata. But it could overlap the symbol defined in the rodata, and it's value plus a constant. .align 3 .globl hello_rodata .set

[Bug binutils/27584] nm riscv: Suppress empty name symbols unless --special-syms?

https://sourceware.org/bugzilla/show_bug.cgi?id=27584 --- Comment #3 from Nelson Chu --- (In reply to Fangrui Song from comment #2) > You can try any C file. Due to label differences, there are always lots of > STB_LOCAL STT_NOTYPE symbols. It seems that GCC uses .L0 while clang uses an > empty

[Bug binutils/27584] nm riscv: Suppress empty name symbols unless --special-syms?

https://sourceware.org/bugzilla/show_bug.cgi?id=27584 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/27566] [RISC-V] relocation truncated to fit: R_RISCV_GPREL_I against aymbol

https://sourceware.org/bugzilla/show_bug.cgi?id=27566 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

[Bug ld/27566] [RISC-V] relocation truncated to fit: R_RISCV_GPREL_I against aymbol

https://sourceware.org/bugzilla/show_bug.cgi?id=27566 --- Comment #2 from Nelson Chu --- Therefore, when we are doing the LUI and PCREL relaxations (GP to symbol or c.lui to symbol, must cross the DATA_SEGMENT), * If "-z relro" isn't set, then we need to reserve at most "MAXPAGESIZE" for the

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 --- Comment #5 from Nelson Chu --- Oh I forgot to add the PR27433 in the comment, so it doesn’t show which commit fixes this PR. commit ebdcad3fddf6ec21f6d4dcc702379a12718cf0c4 Refs: [master], {upstream-write/master},

[Bug ld/24685] [RISCV] R_RISCV_CALL_PLT should not create a canonical PLT in -no-pie mode

https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Nelson Chu changed: What|Removed |Added Resolution|--- |FIXED Status|NEW

[Bug binutils/27158] RISC-V port still has UJ instruction type references

|--- |FIXED CC||nelsonc1225 at sourceware dot org --- Comment #3 from Nelson Chu --- Marked resolved/fixed. -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 --- Comment #3 from Nelson Chu --- Created attachment 13232 --> https://sourceware.org/bugzilla/attachment.cgi?id=13232=edit proposed solution v2 Fixed the conflicts since the v1 patch is too old. After applying this patch, the "call

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 Nelson Chu changed: What|Removed |Added Attachment #13231|0 |1 is obsolete|

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 --- Comment #2 from Nelson Chu --- The attached is the proposed solution. We use a new boolean "restart_relax" to determine if we need to re-run the whole relax passes again from 0 to 2. Once we have deleted the code between relax pass 0 to

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 Nelson Chu changed: What|Removed |Added Target||riscv*-*-* -- You are receiving this

[Bug ld/27433] RISC-V linker might lose relax opportunities since "again" doesn't work as expected

https://sourceware.org/bugzilla/show_bug.cgi?id=27433 --- Comment #1 from Nelson Chu --- Created attachment 13231 --> https://sourceware.org/bugzilla/attachment.cgi?id=13231=edit proposed solution -- You are receiving this mail because: You are on the CC list for the bug.

[Bug ld/27433] New: RISC-V linker might lose relax opportunities since "again" doesn't work as expected

tatus: NEW Severity: enhancement Priority: P2 Component: ld Assignee: unassigned at sourceware dot org Reporter: nelsonc1225 at sourceware dot org Target Milestone: --- We find that the more relax passes, the more chances of relaxations are reduced. Orig

[Bug ld/24685] [RISCV] R_RISCV_CALL_PLT should not create a canonical PLT in -no-pie mode

https://sourceware.org/bugzilla/show_bug.cgi?id=24685 Nelson Chu changed: What|Removed |Added CC||nelsonc1225 at sourceware dot org

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