Hi,
there are machines (in particular those based on AMD CPUs) where
the APIC-ID of the boot CPU's LAPIC is not zero. Instead APIC-ID zero
is apparently assigned to the first IO-APIC. AFAICS we will mis-route
MSI interrupts on such a machine.
The symptom (apart from MSI interrupts not
Hi,
On Fri, Sep 21, 2012 at 11:53:23AM +0200, Mark Kettenis wrote:
there are machines (in particular those based on AMD CPUs) where
the APIC-ID of the boot CPU's LAPIC is not zero. Instead APIC-ID zero
is apparently assigned to the first IO-APIC. AFAICS we will mis-route
MSI interrupts on
On Tue, Sep 18, 2012 at 12:58:23AM +0200, Matthieu Herrb wrote:
On Tue, Sep 18, 2012 at 12:14:45AM +0200, Tobias Ulmer wrote:
Xorg from Fri Aug 31 16:27:51 MDT 2012 worked fine, Xorg from Tue Sep
11 15:42:48 MDT 2012 segfaults:
Can you follow instructions in /usr/xenocara/README to get a
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Date: Fri, 21 Sep 2012 15:00:12 +0200
From: Christian Ehrhardt open...@c--e.de
Hi,
On Fri, Sep 21, 2012 at 11:53:23AM +0200, Mark Kettenis wrote:
there are machines (in particular those based on AMD CPUs) where
the APIC-ID of the boot CPU's LAPIC is not zero. Instead APIC-ID zero
