Re: [casper] I2C and SPI on roach {I,II}

Thanks, David. What voltage levels are on the IIC bus on R and R2? John Hi John. We have a need for an I2C *or* an SPI port on ROACH 1 and 2. There are actual headers on R1 that say SPI and IIC. Are these attached to the PPC? Is there any driver support for them? These do attach to

[casper] Roach clocking question

Hi Casperites, I have a new ADC board (6 channels, 12-bits, 1GSPS) for which I wrote a yellow block. I have the usual option of clocking the FPGA from the sysclk or from the ADC clock, and both options work fine. But when you clock the whole thing from the ADC clock, you get into the

Re: [casper] I2C and SPI on roach {I,II}

What voltage levels are on the IIC bus on R and R2? They are both 3v3. Thanks, David. My pleasure.

Re: [casper] Roach clocking question

Hi Rick the FPGA.  I gather that the software registers are resynch'ed to the fabric clock; is there a way to defeat this resynching, or some other option for switching clocks?  It'd be trivial in Verilog, but I don't see how to do it in Simulink. As you said, all the Simulink signals are