[casper] one_Gbe timing errors

Hi All, I have a Roach2 design using the one_Gbe yellow block. I intermittently have timing errors in this block seemingly unrelated to the design. Below is a TS_mac_rx_clk timing constraint failure. The FPGA is running at 125 MHz and approximately 50% of the resources are currently being utiliz

Re: [casper] FFT speed optimizations

Hi Dave, thanks for this info. >> One thing you could try is to add even more delay stages so that you have >> more leftover after some get combined into the macrocells. That’s exactly what I did. If I understand correctly then the maximum pipeline depth of a DSP48 is four, above that all

Re: [casper] FFT speed optimizations

Hi Jack, thanks for your help. >> You could always add your own constraint file using the "UCF" block. I have to admit, I’m not aware of a UCF block. Is that a Simulink block? We are using Simulink R2013a, I couldn’t find it in the browser. Thanks, cheers Guenter From: Jack Hick

Re: [casper] FFT speed optimizations

Hi Guenter, It's a block in the xps (yellow block) library. It's been in the library a while, but you might not have it if you're using a really old version. Cheers Jack On Fri, 23 Sep 2016, 04:54 Guenter Knittel, wrote: > Hi Jack, > > > > thanks for your help. > > >> You could always add your

Re: [casper] FFT speed optimizations

> On Sep 23, 2016, at 04:17, Guenter Knittel wrote: > > I guess normally one would do this by going to the Function Block Parameters > and setting > > the latencies accordingly. However, I have made so many manual ad-hoc changes > to the > > Simulink model that this is not an option any more