Hi James, Michael, and Vereese,
Thanks for your reply. I have read the timing report to find the failing paths,
and tried to add delay blocks or increasing adder / multiplier latency. It
works well but not always, especially for timing errors in some yellow blocks,
for instance
I will try Sma
Hello Yunpeng,
Just to echo what Michael and Vereese said - those tools can help you get a
bit more insight into what's going on, and how badly your timing problem
is, but the timing report should tell you how by how much you're missing
timing (should be some nanosecond value).
If it's just a sma
Hi Yunpeng, all,
I recently wrote a memo which describes how you can use Xilinx SmartXplorer to
help with timing issues. Have a look on the casper wiki in the Memos section:
https://casper.berkeley.edu/wiki/images/f/f8/SmartXplorer_memo.pdf . It isn’t a
free pass – you need to get fairly close
Hi Yunpeng,
You can use Xilinx's PlanAead tool to help with the timing errors. You can
place your PFB in a "pblock" which helps with timing. I haven't worked with
this in awhile but there's a tutorial on the CASPER wiki here:
https://casper.berkeley.edu/wiki/Tutorial_PlanAhead
I hope that helps
Dear all,I am using ROACH2 to develop digital receiving backend, but I often
encounter timing errors when I run casper_xps toolflow. I wonder if there is
any general solution to these timing errors.Thanks a lot,Yunpeng
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