[casper] FPGA boards - Donation.

Dear CASPER team, Seasons greetings.. I am looking for CASPER FPGA board (ROACH 1 or 2)+ 2 Ch ADC. If anyone willing to donate it. Please let us know. Will write you more about the project in detail. Thanks and regards Indrajit -- You received this message because you are subscribed to the

Re: [casper] ROACH 1 root file system image

Dear Dr Colm Bracken,I shared the image file here.https://drive.google.com/file/d/13MJ5ad3qi0VIggE98t6lKSJPtqeOScb7/view?usp=drivesdkThanks and regards Indrajit On 27 Oct 2023 19:28, Colm Bracken wrote: Caution: This email originated outside IIA. Hello All,I hope everyone is well.Does anyone have

Re: [casper] Save the raw data output from the ADC

Dear Wang, I use ROACH 1 with iADC.  Block library's may be different. Logic you can use it by replacing the ADC block with your ADC library and 10 GBe library. Thanks and regards Indrajit On 08/03/23 1:46 pm, Wang wrote: Caution: This email originated outside IIA. Hi Indrajit, May I

Re: [casper] Save the raw data output from the ADC

Hi Wang, Generally, I use Burst mode (Non continues ) of RAW voltage recording for ADC testing and other testing, Herewith I shared the design file which packs the raw voltage (iADC) into the 10 Gbe. https://drive.google.com/file/d/17766ANxnbz9Um-RdTiUrtZl5KOQAhNqq/view?usp=sharing Thanks a

Re: [casper] RA Instruments using CASPER hardware and tools

Dear Morag, GLOSS (Gauribidanur LOw frequency Solar Spectrograph) ROACH 1 + iADC Gaauribidanur pulsar array (ROACH + QUAD ADC). Thanks and regards Indrajit On 31/08/22 4:23 pm, Morag Brown wrote: Caution: This email originated outside IIA. Ciao dalla Sardegna, collaborati! I'm hoping to

[casper] CASPER Hardware page showing 404 error

Dear Casper team, The link to the following hardware page is showing error 404 on github webpage: https://github.com/casper-astro/casper-hardware/blob/master/ADC2x400-14 and old CASPER : http://casper.astro.berkeley.edu/wiki/Hardware Any updates on that. Season's Greetings Thanks and regards Ind

[casper] TDM data FIR LP filter

Hello all, Medicina team / GMRT team Is there any TDM (X64 ADC )data 32 tap FIR LP filter green block or custom Xilinx block. I am looking into the VEGAS design but it is a parallel streams of the data going into the filter section. Thanks and regards Indrajit Barve indra...@iiap.res.in

[casper] SNAP board writing and reading the registers issue.

ailed.\n\t' 162 'Request: %s\n\tReply: %s' % --> 163 (request.name, self.host, request, reply)) 164 elif reply.arguments[0] == katcp.Message.INVALID: 165 raise KatcpRequestInvalid( KatcpRequestFail: Request read on host 192.168.41.159 failed. Request: ?read payload_length 0 4 Reply: !read fail

Re: [casper] SNAP getting started and error on block placement

Hi Jack and all, Longback I used with Matlab 2016b and Xilinx Vivado 2016.4 , But unfortunately that PC disk got into issues, So some one using with the above version of matlab and Vivado can share their mlib-devel folder. Thanks and regards Indrajit Barve indra...@iiap.res.in (mailto:indra

Re: [casper] ROACH Network is unreachable

Hello All, >From my experience with the similar situation format the SD card and load the >Linux image newly and set it for acquisition. Indrajit Barve indra...@iiap.res.in (mailto:indra...@iiap.res.in) 080-22541492 (tel:080-22541492) On Jun 21 2019, at 10:43 am, David MacMahon

[casper] casperfpga package issue.

ilename = self.bitstream 279 rv = self.transport.upload_to_ram_and_program( --> 280 filename=filename, wait_complete=wait_complete, chunk_size=chunk_size) 281 if not wait_complete: 282 return True TypeError: upload_to_ram_and_program() got an unexpected keyword argument 'chunk_size' ++

Re: [casper] Data-Width Conversion in FIFO

Intialisation something going wrong and creating the broken link. Can you please check. Hello Jack , David Thanks for your inputs. Indrajit Barve indra...@iiap.res.in (mailto:indra...@iiap.res.in) 080-22541492 (tel:080-22541492) On Apr 25 2019, at 6:12 pm, Andrew Martens wrote: > Hi Indra

[casper] Data-Width Conversion in FIFO

Hello all, I would like to implement a FIFO with input port data type depth and width of 2048 X 32 and output port data type 1024 X 64. Basically looking a similar module like this https://www.xilinx.com/support/documentation/application_notes/xapp261.pdf . or how to implement / configure Data