[casper] Create a full PL pdi for AMD Versal SoC

Hi All, Happy new year! I'm working on the 400G Ethernet test on vpk180 board, which is based on the AMD Versal SoC chip. To do the test remotely (and also to port the casper toolflow on this board later), I created a Ubuntu image for

Re: [casper] Debugging on MPSOC with PYNQ image

PL if you > enable them. > > > -Jeb > > —— > Dr. J.I. Bailey, III (Jeb) / Project Scientist > Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of > Physics, UCSB > jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone > > On Nov 2, 2020,

Re: [casper] Debugging on MPSOC with PYNQ image

Wei, >Is there any chance this workaround is related to needing cpu.idle=1 on > your kernel command line? I know trying to use the system ilas will cause > the PS side to hang without it. > > -Jeb > > Sent from my mobile. > > On Nov 2, 2020, at 15:57, Wei Liu wrote: > >

[casper] Debugging on MPSOC with PYNQ image

Hi Casperites, I'm working on porting casper toolflow on ZCU111. I want to share some debugging experiences, which may be helpful. We have PYNQ image running on the PS part, which is based on Ubuntu18.04. I found PL registers can't be accessed after the bit file is downloaded via JTAG. Because

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

III (Jeb) / Project Scientist > Mazin Lab <http://web.physics.ucsb.edu/~bmazin/> / Department of > Physics, UCSB > jebbailey.com / +1 (734) 389-5143 / skype:spacecolonyone > > On Oct 7, 2020, at 11:46 AM, Wei Liu wrote: > > Hi Colm, > > Currently, I put the code

Re: [casper] PYNQ+Vivado 2019.2+RFDC Block

share that? Or does he intend to make it > available on the CASPER Github? > > Thanks a million, > Colm > > On Wed, 7 Oct 2020 at 02:59, Dan Werthimer wrote: > >> >> >> hi jeb, >> >> regarding your ZCU111 RFDC question: >> here's some info t