Hi Dave, John,
Thanks for the replies. I don't think it was a boolean problem (I initially
suspected this and double checked things with the port update).
Just after I sent the email, I replaced the yellow block register with a
Xilinx constant, and it seemed to compile. I've now replaced the
Hi all,
I have a strange error that arises after a small change to a design:
I have used the sync pulse to reset a counter, that in turn (together with
a comparator coupled to a register) produces a higher frequency pulse for
use in snap blocks i.e. to write the snap block data more frequently
Hi.
Maybe a boolean check box needs checked somewhere in your new logic?
John
Hi all,
I have a strange error that arises after a small change to a design:
I have used the sync pulse to reset a counter, that in turn (together with
a comparator coupled to a register) produces a higher
Hi, Charles,
Is it when you click OK on a block's mask dialog or when you run update
diagram or ???
Maybe you can find additional details in the model_sysgen.log or
model_sysgen_warning.log or model_sysgen_error.log files? It would
really help to know which block or file is causing this
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