回复: [casper] Question about the RFSoC Clock Configuration

point number value and try to test the ADC with signal generator. Best regards, Yunfan 发件人: casper@lists.berkeley.edu 代表 Bishnu Kumar Sharma 发送时间: 2024年2月28日 19:57 收件人: casper@lists.berkeley.edu 抄送: Yunfan ZHANG 主题: Re: [casper] Question about the RFSoC Clock Configuration Hi Yunfan, I also

Re: [casper] Question about the RFSoC Clock Configuration

Hi Yufan, Sorry this did not resolve your issues. I believe I see the issue now and am sorry I did not catch this earlier. In your previous screenshots for the configuration of the RFDC the PLL reference clock input is set to 245.76 MHz when it should be set to 491.52 MHz. The LMX file you are

Re: [casper] Question about the RFSoC Clock Configuration

Hi Yunfan, Could you please try the `m2021a-dev` branch of `mlib_devel` and see if it helps resolve your issues with setting up the clock configuration? This development branch has new changes and adjustments that make simpler and s