Hey Suraj.
I've been working on Verilog code that requires the application of a
MAXDELAY constraint to an 8 bit data bus output from a register
explicitly forced into the Input/Output Buffer. When I apply the
constraint to the whole bus, PAR results show that the Xilinx tools
attempt to a
Hello all,
I've been working on Verilog code that requires the application of a
MAXDELAY constraint to an 8 bit data bus output from a register
explicitly forced into the Input/Output Buffer. When I apply the
constraint to the whole bus, PAR results show that the Xilinx tools
attempt to
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