Re: [casper] one_GbE on roach-2 fpga

Hi Ioana Thanks Dave! I have fixed the typo and push it to github. ( https://github.com/casper-astro/mlib_devel/commit/cb1790fa0e3c750b3f73cf82e80555c1b5f79edc ) Regards Henno On Sat, Jan 12, 2013 at 1:47 AM, Ioana Alexandra Zelko < ioana.ze...@gmail.com> wrote: > It worked. Thank you! > > > >

Re: [casper] one_GbE on roach-2 fpga

It worked. Thank you! On Fri, Jan 11, 2013 at 2:57 PM, David MacMahon wrote: > Hi, Ioana, > > On Jan 11, 2013, at 9:34 AM, Ioana Alexandra Zelko wrote: > > > ERROR:HDLCompiler:597 - > "/home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_base/pcores/gbe_udp_v1_00_a/hdl/

Re: [casper] one_GbE on roach-2 fpga

Hi, Ioana, On Jan 11, 2013, at 9:34 AM, Ioana Alexandra Zelko wrote: > ERROR:HDLCompiler:597 - > "/home/omniscope/fftt/models/x5_devel/Trivial_tests/1gbe/small_test/XPS_ROACH2_base/pcores/gbe_udp_v1_00_a/hdl/verilog/gbe_udp.v" > Line 227: Module gbe_cpu_attach does not have a parameter named C_

Re: [casper] one_GbE on roach-2 fpga

Yes, there are a couple of counters and delays On Fri, Jan 11, 2013 at 12:19 PM, G Jones wrote: > Just a wild guess (I haven't looked at the model file)... do you have > any register/delay/counter in your design? You need at least one > xilinx block in your simulink diagram that requires a clock

Re: [casper] one_GbE on roach-2 fpga

Just a wild guess (I haven't looked at the model file)... do you have any register/delay/counter in your design? You need at least one xilinx block in your simulink diagram that requires a clock otherwise the synthesis will strip out your simulink clock and the design won't compile. On Fri, Jan 11

Re: [casper] one_GbE on roach-2 fpga

Hi Ioana I have done 2 successful compiles: one with only a one_GbE yellow block and one with a one_GbE yellow block + ten_GbE. Is it possible to send me your model file to compile? Regards Henno On Fri, Jan 11, 2013 at 5:47 AM, Ioana A Zelko wrote: > Dear Casper Group, > > > We are trying t

Re: [casper] one_GbE on roach-2 fpga

Hi, Ioana, I think the details of the error were output earlier than the snippet you included. They might also be in platgen.log, which you can find in your /XPS_ROACH2_base directory. My guess is that it's a bug in the 1 GbE yellow block. Which mlib_devel version are you using? Dave On Ja

[casper] one_GbE on roach-2 fpga

Dear Casper Group, We are trying to set up data transmission from the fpga through its 1gbe ethernet port. For this, we tried using the one_GbE block from the library, with its default settings. However, when we try to compile a small design that has basically just the one_GbE with its require