There a re a couple of systems that used a 68000 in a Unix type environment. I
have worked on both.The first is an Altos ACS68000 system that used a 68000 and
4 (four, count'em) 68451 mmu units. The way it did the memory allocation was
to use stack probes to trip up a memory fault interrupt.
It is the follow on to the Microdata 1600 that Basic four used in its
first business machines.
He has two machines and at least a disk for the system, I think.
Basic Four became MAI. They were noted for having a multi user basic
system for business very early on.
Also it survive(s) today
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Paul
Koning
Sent: 13 July 2015 17:03
To: General Discussion: On-Topic Posts
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
the RICM)
On Jul 13, 2015, at 8:35 AM, Jay
From: Rich Alderson
Changing from PDP-8 operation to LINC operation was a matter of a
physical switch.
Err, not according to the Small Computer Handbook (1967 Edition), which
covers the LINC-8 in detail - at least, as I understand it? See, for instance,
pg. 307 A LINC HALT
Seconded; I was just leafing through A DEC view of hardware systems
design again last week and I had noticed that footnote and was wondering
myself ... the PDP-3 must be the rarest of them all :O I wonder if there
are any surviving leftovers?
Best,
Sean
On Tue, Jul 14, 2015 at 1:04 AM, Paul
On Jul 13, 2015, at 8:52 PM, Johnny Billquist b...@update.uu.se wrote:
On 2015-07-13 21:16, Rich Alderson wrote:
...
[2] With memory management, 18 or 22, in 16-bit segments. Late models could
use separate instruction and data segments, for a total of 128KB in use
at
one
On Jul 14, 2015, at 7:53 AM, Noel Chiappa j...@mercury.lcs.mit.edu wrote:
From: Jay Jaeger
I am going to attempt to do the same for IBM's 1410 computer - a really
big effort.
Now, the IBM machine you (or someone) should _really_ do is the IBM Stretch
(7030); although judged a
My work has been using structural models, at the gate level, in VHDL
(Verilog would be fine, too, of course). Individual components (for
example, a piece of an IBM SMS card, or in my existing case, gates made
available to student engineers that were actually individual
gates/chunks of DTL chips)
On 7/13/2015 10:02 AM, Paul Koning wrote:
A different approach is to reproduce the actual logic design. FPGAs
can be fed gate level models, though that’s not the most common
practice as I understand it. But if you have access to that level
of original design data, the result can be quite
On 7/14/2015 9:46 AM, Jay Jaeger wrote:
My work has been using structural models, at the gate level, in VHDL
(Verilog would be fine, too, of course). Individual components (for
example, a piece of an IBM SMS card, or in my existing case, gates made
available to student engineers that were
On Jul 14, 2015, at 11:46 AM, Jay Jaeger cu...@charter.net wrote:
...
Using the structural / gate level techniques, one does run into some
issues, most of which have (or will probably have) solutions:
1) R/S latches composed of gates in a combinatorial loop. The problems
this causes
Date: Mon, 13 Jul 2015 01:52:09 -0400
From: Kip Koon computer...@sc.rr.com
Subject: RE: PDP-12 at the RICM
Hi Michael,
I would be most interested in finding out more about this effort. Do you
have ongoing pictures documenting this effort? I'd love to have a PDP 8,
11, 12 someday, but I
Date: Sun, 12 Jul 2015 16:10:10 -0500
From: Jay Jaeger cu...@charter.net
Subject: Re: PDP-12 at the RICM
BTW, if there are particular cards you need / are bad, in addition to
the actual PDP-12, I have the backplanes and cards for a 2nd one, so if
you need something, we could probably work
I'm not even sure what the machine is. Can you give
a little more information on what it is?
Dwight
Subject: Re: Linear Power Supply (Conversion Equipment Corp) from a basic
four 510
To: cct...@classiccmp.org
From: a...@ardiehl.de
Date: Mon, 13 Jul 2015 18:28:56 +0200
Thanks, yes you
On 7/13/2015 4:59 PM, Michael Thompson wrote:
Date: Mon, 13 Jul 2015 01:52:09 -0400
From: Kip Koon computer...@sc.rr.com
Subject: RE: PDP-12 at the RICM
Hi Michael,
I would be most interested in finding out more about this effort. Do you
have ongoing pictures documenting this effort? I'd
Thanks, yes you are right. And it is fixed now. Would have been more
easy with the schematics on hand.
But the 510 does not seem to start, may be the mini test program i have
(to boot from terminal) only works with the model 210 and not with the
510. (http://basicfour.de/cpu/small/index.html)
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of ANDY HOLT
Sent: 14 July 2015 10:20
To: General Discussion: On-Topic and Off-Topic Posts
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
the RICM)
- Original
I'm missing something in this discussion, I think.
HDL's (take your pick) are just programming languages like FORTRAN or C
with different constraints. What's the point of going to all the
trouble of doing an FPGA implementation of a slow old architecture, when
pretty much the same result
Hello Everybody
In the course of doing the artwork for 8/e
type B I have turned up some more variations.
The list now looks like this:
1. Switch position markings
2. Line round switch area
3. The EMA title block isolated from the other titles
4. Lines between groups
On 07/14/2015 10:55 AM, Noel Chiappa wrote:
I guess I don't know the 6600 that well (I have the book, and have skimmed it
in the past). What are the novel features in the 6600 that were widely
adopted by other machines? (I listed the Atlas because of paging, and the 801
because of RISC.)
On 07/14/2015 11:14 AM, Alan Hightower wrote:
Determinism. Unless you run your software simulator bare-metal - which
most aren't - cycle accuracy is always a race. Before you say modern
processors are 100,000 times faster than emulated ones - so just spin
wait until the next virtual time tick,
On Jul 14, 2015, at 1:55 PM, Noel Chiappa j...@mercury.lcs.mit.edu wrote:
From: Paul Koning
I have a hard time coming up with other machines with the same level
of impact/influence, in terms of CPU internal architecture. Maybe
Atlas, or the 801?
CDC 6600, of course.
I guess I don't
On 07/14/2015 02:05 PM, Jay Jaeger wrote:
Going all the way back to at least the IBM 7090, and presumably the 709,
though I have not actually checked. The B5000 had IO processors as well.
Again, you're missing the point. The system *starts* with a PPU and
loads the CPU up to run. OS was
Hi
Oscar Vermeulen managed to get an 8/I replica going using a
Raspberry Pi and Bob's code.
You do have to hook into the code of course. I want to do an 8/e the
same way.
Regards Rod
On 14/07/2015 20:25, Paul Koning wrote:
On Jul 14, 2015, at 2:42 PM, Rod Smallwood
On Jul 14, 2015, at 3:27 PM, tony duell a...@p850ug1.demon.co.uk wrote:
That sounds like a bug in the original. If you have a set of flops clocked
by some signal, and it matters that the
outputs don’t all change at the same time, then the original wasn’t reliable
either.
It is
Again, you're missing the point.
This was a fairly specific CDC Cyber thing - not a widely adopted idea
in the industry, as was originally asked for.
The channel controller/director idea, on the other hand, was very
widely adopted.
--
Will
On Jul 14, 2015, at 2:42 PM, Rod Smallwood rodsmallwoo...@btinternet.com
wrote:
Back at a more general level. To my way of thinking what Bob Supnik did in
software can be extended by producing a hardware replica vehicle for his code
to give the illusion that the original system has been
That sounds like a bug in the original. If you have a set of flops clocked
by some signal, and it matters that the
outputs don’t all change at the same time, then the original wasn’t reliable
either.
It is very poor design, and not something that I would do, but it certainly was
done in
...I/O processors.
I do not think you can claim that the 6600 I/O processors were all
that new. Many (most?) of the 1960s mainframes before the 6600 had
channel controllers.
--
Will
Hi Tom
I had thought somebody had done one (or it was part of a kit)
However I cant find
anything about it. So lets have a look at your scan.
Regards
Rod
On 14/07/2015 19:44, Tom Moss wrote:
Hi Rod,
Any chance I could commission you to do an Altair 8800 panel?
The silkscreen has
Hi folks,
I'm looking to buy at whatever price is fair a GRiD Compass (Not the DOS
based ones) computer of any model-- and perhaps condition- as I may be able
to repair
I recently missed an ebay auction, which was sad.
Let me know,
Thanks,
- Ian
-
Background.
About a year or so, I
On 7/14/2015 11:27 AM, Paul Koning wrote:
On Jul 14, 2015, at 11:46 AM, Jay Jaeger cu...@charter.net wrote:
...
Using the structural / gate level techniques, one does run into some
issues, most of which have (or will probably have) solutions:
1) R/S latches composed of gates in a
On 2015-07-14 19:52, Noel Chiappa wrote:
On Jul 13, 2015, at 8:52 PM, Johnny Billquist bqt at update.uu.se
wrote:
??? What segments??? The PDP-11 have a plain simple page table. No
segments anywhere in sight. And each page is 8K.
I know the processor handbook calls them
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five clocks delayed from each other (more
commonly known as clock phases).
IBM used this method as well on many of their machines.
--
Will
On 07/14/2015 04:49 PM, Jay Jaeger wrote:
Not necessarily. For example, it is impossible to find an IBM 1410, as
far as I know. But there ARE 1415 consoles I knew of a while back, and
there are certainly 729s and 1403 printers and 1402 card read/punch
units up and running.
There are plenty
On 7/14/2015 11:16 AM, ben wrote:
Here is the link you have been waiting for, IBM 1130 in FPGA and in the
FLESH.
http://ibm1130.blogspot.ca/
Ben.
Thanks for that link. It looks very interesting after a quick glance. I
am sure that I will run into many of the same issues with the SMS
On 07/14/2015 07:11 PM, William Donzelli wrote:
I suppose you could view it that way. There were CPU-less 6000 boxes, but
no PPU-less ones.
Were the CPU-less 6000 boxes at least connected to normal 6000s with
CPUs using shared ECS, or could they really be completely independent
units using
Wow, Landon's still at it after 12 years?
You'd have thought he'd have a life by now...
On 14 July 2015 at 21:38, Todd Goodman t...@bonedaddy.net wrote:
Anyone contemplating dealings with Mr. Landon should check Google and
archives of this mailing list.
He's a thief.
* drlegendre .
On 07/14/2015 03:42 PM, William Donzelli wrote:
That's true--but at the time, CDC's design made a huge amount of sense. The
CPU was left to do what it did best--crunch numbers without the burden of
managing the I/O activity and responding to interrupts. In that sense, the
CPU was treated as
Almost sounds like the CPU was kind of an attached processor - similar
to the way vector processors have been implemented by IBM and others.
On 7/14/2015 5:28 PM, Chuck Guzis wrote:
On 07/14/2015 02:53 PM, William Donzelli wrote:
Again, you're missing the point.
This was a fairly specific CDC
On 2015-07-14 16:09, Paul Koning wrote:
On Jul 13, 2015, at 8:52 PM, Johnny Billquist b...@update.uu.se wrote:
On 2015-07-13 21:16, Rich Alderson wrote:
...
[2] With memory management, 18 or 22, in 16-bit segments. Late models could
use separate instruction and data segments, for a
On 07/14/2015 06:10 PM, Jay Jaeger wrote:
Almost sounds like the CPU was kind of an attached processor - similar
to the way vector processors have been implemented by IBM and others.
I suppose you could view it that way. There were CPU-less 6000 boxes,
but no PPU-less ones.
--Chuck
I suppose you could view it that way. There were CPU-less 6000 boxes, but
no PPU-less ones.
Were the CPU-less 6000 boxes at least connected to normal 6000s with
CPUs using shared ECS, or could they really be completely independent
units using their own ECS?
--
Will
On Jul 14, 2015, at 4:41 PM, Chuck Guzis ccl...@sydex.com wrote:
On 07/14/2015 10:29 AM, Paul Koning wrote:
The accuracy of the FPGA depends on the approach. If it’s a
structural (gate level) model, it is as accurate as the schematics
you’re working from. And as I mentioned, that
The 12-bit computer that I translated originally had *independent* 1
micro-second clocks in each of four racks. The processor derived a 3
micro-second clock from that, but also a second clock that was out of
phase with the CPU master clock, used to sync. signals coming in from
the other racks
On 7/14/2015 7:36 PM, Jon Elson wrote:
On 07/14/2015 07:44 PM, William Donzelli wrote:
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five clocks delayed from each other (more
commonly known as clock phases).
IBM used this method as well on many of
On Tue, Jul 14, 2015 at 3:28 PM, tony duell a...@p850ug1.demon.co.uk wrote:
If you mean 6 different clock sources (i.e. clocks delayed from each other,
etc) then that
is not typical of a 1970s minicomputer in my experience.
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
From: Johnny Billquist
While the pages are variable in length, each page starts at an 8K
virtual address boundary.
Which is another difference between PDP-11 'pages', and real pages as used on
every other machine of the period which had virtual memory: normally, page
sizes were
On 7/14/2015 7:31 PM, Chuck Guzis wrote:
Seymour Cray should have used kinetic sculptures on his machines as part
of eye candy, I guess. Or maybe more chrome...
You got a nice love seat. I could see a early cray style maching in a FPGA
but what good is number crunching if you don't have the
On 07/14/2015 06:55 PM, Jay Jaeger wrote:
Architecturally, it was pretty much the last of its kind: the last of
the BCD decimal arithmetic machines, which also makes it interesting.
It has also become much more obscure than the 1401, which it followed,
because not nearly as many were made and
Hey Kip
I can't help you with the software, but I just finished an Altair
restoration (my first) a few months ago, and am still interested in getting
the machine connected and actually doing something interesting. The Altair
was almost totally below the radar by the time I really started getting
I think a lot of things drive the popularity of the PDP-8 from nostalgia to
historicity to perhaps the relative simplicity of the CPU to understand as
a design example in computer architecture ... IMO the machine is just a bit
too limited to be much fun to program in assembly ... although maybe
In the 7000 series, the 1410 equivalent was the 7010 - architecturally
compatible, ran the same software, but implemented in 7000 series
technology. It came along in 1962. So that was really the last one to
be introduced of its ilk.
Other than clones and the like (e.g., from folks like
On Tue, Jul 14, 2015 at 9:58 AM, Jay Jaeger cu...@charter.net wrote:
I wonder if there is anywhere near enough information available to do a
Stretch.
There's enough information to develop a architecturally equivalent
system, either in software or hardware, but AFAIK not anywhere near
enough to
That's an interesting argument against using FPGAs in this sort of
application; definitely food for thought. That said, from my (admittedly
limited hobbyist and academic exposure) to FPGAs, I would expect the bulk
of of whatever's being implemented would be fairly device-agnostic ...
certainly you
As well, some early microprocessors used multiple clocks i.e. the TMS9900.
Best,
Sean
On Tue, Jul 14, 2015 at 8:04 PM, Eric Smith space...@gmail.com wrote:
On Tue, Jul 14, 2015 at 3:28 PM, tony duell a...@p850ug1.demon.co.uk
wrote:
If you mean 6 different clock sources (i.e. clocks
Johnny Billquist wrote:
On 2015-07-14 19:52, Noel Chiappa wrote:
On Jul 13, 2015, at 8:52 PM, Johnny Billquist bqt at
update.uu.se wrote:
??? What segments??? The PDP-11 have a plain simple page
table. No
segments anywhere in sight. And each page is 8K.
I know the
On 7/14/15 9:22 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination
On 7/14/2015 11:07 PM, Fred Cisin wrote:
On Wed, 15 Jul 2015, Kip Koon wrote:
Hi Guys,
I have finally decided to restore my original Altair 8800 which has
been in
storage for over 30 years. Does anyone have a copy of Microsoft's
Multiuser
Disk Extended Basic for the Altair 8800? When I was in
My experience of FPGAs is that if you design a circuit for an FPGA it will
work. If you take an existing design
feed it into a schematic capture program and compile it for an FPGA then it
won't.
Actually, you can, and I have done so - provided that the original
machine was slow
On Wed, 15 Jul 2015, Kip Koon wrote:
Hi Guys,
I have finally decided to restore my original Altair 8800 which has been in
storage for over 30 years. Does anyone have a copy of Microsoft's Multiuser
Disk Extended Basic for the Altair 8800? When I was in college in '79 to
'81, in the computer
The 8086 had four segment registers:
CS - Code segment, used with IP register
DS - Data segment
SS - Stack segment, used with SP and BP registers
ES - Extra segment, used with DI for string instructions as
destination (DS:SI
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination (DS:SI as source)
You could override
On 7/14/15 9:53 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
destination
ATT has gone wierded out on attachments for the moment, so I'm dumping all this
into a long text ramble
Jim:
Please forward these observations to the appropriate parties, copying me. I am
having trouble sorting out who started the thread and who is receiving replies.
I will respond directly
Buchholz's 'Planning a Computer System: Project Stretch' is a good start,
but I'd be interested in hearing about any other technical sources that
folks know about. -C
amturing.acm.org/Buchholz_102636426.pdf
On Tue, Jul 14, 2015 at 10:58 AM, Jay Jaeger cu...@charter.net wrote:
I wonder if there
I have an interesting brochure, that is not on bitsavers (that I can find),
for the Digital IDACS 11/07 Industrial Control System
This is a stand-alone-capable UNIBUS PDP 11 industrial system made for
analog and digital inputs with RSX-11C software, FORTRAN, PDP-11 DOS,
COMTEX-11.
If this is
I wonder if there is anywhere near enough information available to do a
Stretch.
JRJ
On 7/14/2015 6:53 AM, Noel Chiappa wrote:
From: Jay Jaeger
I am going to attempt to do the same for IBM's 1410 computer - a really
big effort.
Now, the IBM machine you (or someone) should
yes, but the only software that survives are diagnostic listings.
I tried and gave up trying to get the software from the person who saved the
Livermore Stretch
Is he a typical hoarder? He can do a better job saving the stuff
than a museum?
--
Will
I have a document that describes how to convert 709 Fortran to
7090-compatible Fortran. Might help imply what you'd need generally when
compared to a 709, using that as a starting point.
On Tue, Jul 14, 2015 at 12:21 PM, Al Kossow a...@bitsavers.org wrote:
yes, but the only software that
On 7/14/2015 10:22 PM, Fred Cisin wrote:
The 8086 had four segment registers:
CS- Code segment, used with IP register
DS- Data segment
SS- Stack segment, used with SP and BP registers
ES- Extra segment, used with DI for string instructions as
On 07/14/2015 02:53 PM, William Donzelli wrote:
Again, you're missing the point.
This was a fairly specific CDC Cyber thing - not a widely adopted idea
in the industry, as was originally asked for.
The channel controller/director idea, on the other hand, was very
widely adopted.
That's
Sometimes it is fun to be a relative expert on an obscure branch of
knowledge that few people are even aware of.
I worked on one when I was a student, as an operator, programmer and
systems programmer. Tweaked its FORTRAN compiler to spit out text error
messages instead of just error codes. The
On 07/14/2015 07:44 PM, William Donzelli wrote:
IIRC, the KB11 processors used in the DEC 11/45 and 11/70 (and other
related systems) used five clocks delayed from each other (more
commonly known as clock phases).
IBM used this method as well on many of their machines.
On the system 360 CPUs,
Meh. You take your machines and I'll take mine. :) The IBM 1410 is a
machine I know well, so I know how it is supposed to work, and I have
detailed information in the form of the ALD's and the CE training
materials to go with it, plus software including diagnostics and
operational software I can
Yes, the S/360 had packed decimal - but much more limited in length, and
no wordmark concept.
The 7070 and 7080 were contemporary with the 1410, not after it. They
did not follow it. While data representations were somewhat similar,
the instruction formats were very different.
he 7080 (which
On 07/14/2015 09:16 PM, Jay Jaeger wrote:
Other than clones and the like (e.g., from folks like Honeywell), I'm
not aware of any other machines with a similar architecture to the 1401
and 1410. Name them?
Well, how about a bit-addressable, variable field length machine that
had not only
Back at a more general level. To my way of thinking what Bob Supnik did
in software can be extended by producing a hardware replica vehicle for
his code to give the illusion that the original system has been
recreated. A sort of machine Turing test if you will.
Rod Smallwood
/
/
/On
Kind reader
I have two manuals labelled STSC APL*PLUS System for VAX VMS: User's
Manual and Reference Manual which were sent to me a number of years ago
as paper copies - I now have the ability to easily scan these into PDF
format.
Would these be of interest to anyone? There is a PC version
-Original Message-
From: cctalk [mailto:cctalk-boun...@classiccmp.org] On Behalf Of Chuck
Guzis
Sent: 14 July 2015 18:17
To: gene...@classiccmp.org; discuss...@classiccmp.org:On-Topic and Off-
Topic Posts
Subject: Re: Reproducing old machines with newer technology (Re: PDP-12 at
On Jul 13, 2015, at 8:52 PM, Johnny Billquist bqt at update.uu.se wrote:
??? What segments??? The PDP-11 have a plain simple page table. No
segments anywhere in sight. And each page is 8K.
I know the processor handbook calls them 'pages', but I can't think of any
other machine
From: Paul Koning
I have a hard time coming up with other machines with the same level
of impact/influence, in terms of CPU internal architecture. Maybe
Atlas, or the 801?
CDC 6600, of course.
I guess I don't know the 6600 that well (I have the book, and have skimmed it
On 07/14/2015 10:35 AM, ben wrote:
I've run the Cyber emulator as well as various SIMH emulators from time
to time, but it's just not the same as the real thing--it's not even
remotely the same.
You can still the old computer blinking lights movie props.
On a Cyber? What blinking lights?
On 7/14/2015 11:17 AM, Chuck Guzis wrote:
I'm missing something in this discussion, I think.
HDL's (take your pick) are just programming languages like FORTRAN or C
with different constraints. What's the point of going to all the
trouble of doing an FPGA implementation of a slow old
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