From: Guy Sotomayor: Tuesday, March 29, 2016 8:27 PM
These 3 wires were *really* short. Nothing I did found them until I came
across a “trick” which is to zoom out so the board is tiny and then with
the route tool active, just “click” on spot on the board. In short order I
found all 3 remaining
I've never used EagleCAD but some CAD packages let you turn off all routed
lines
On Tue, Mar 29, 2016 at 5:25 PM, Paul Koning wrote:
>
> > On Mar 29, 2016, at 8:18 PM, Guy Sotomayor wrote:
> >
> > I just finished laying out the board for the MEM11A. The last roadblock
> was figuring out
> >
> On Mar 29, 2016, at 5:50 PM, Ethan Dicks wrote:
>
> On Tue, Mar 29, 2016 at 8:25 PM, Paul Koning wrote:
>>> On Mar 29, 2016, at 8:18 PM, Guy Sotomayor wrote:
>>> ...autorouter on Eagle 7.5, so I did this all by “hand”
>>> (at just under 2000 wires it took a while).
>>
>> I can imagine. Han
On Tue, Mar 29, 2016 at 8:25 PM, Paul Koning wrote:
>> On Mar 29, 2016, at 8:18 PM, Guy Sotomayor wrote:
>> ...autorouter on Eagle 7.5, so I did this all by “hand”
>> (at just under 2000 wires it took a while).
>
> I can imagine. Hand-routing tends to produce much better results;
Yep.
> the au
> On Mar 29, 2016, at 8:18 PM, Guy Sotomayor wrote:
>
> I just finished laying out the board for the MEM11A. The last roadblock was
> figuring out
> where the last 3 unrouted wires were. EagleCAD didn’t make it easy to find
> them and I
> haven’t quite figured out how to use the autorouter o
I just finished laying out the board for the MEM11A. The last roadblock was
figuring out
where the last 3 unrouted wires were. EagleCAD didn’t make it easy to find
them and I
haven’t quite figured out how to use the autorouter on Eagle 7.5, so I did this
all by “hand”
(at just under 2000 wires
Just wanted to let folks know where the MEM11A (as opposed to the UMF11) is.
All of the verilog code is written for the CPLD and I’ve simulated full unibus
transactions
to the FRAM and everything seems to work.
I’m almost done with schematic entry. I just have a few things to clean up and
veri
On Thu, Mar 17, 2016 at 3:35 PM, Guy Sotomayor wrote:
> I’m planning on doing a 4 layer board so I can avoid having routing issues
> due to 3 different
> power supply voltages (yea, modern low voltage design meets 5v). I haven’t
> done a 4 layer
> design before, so I’m in for a bit of learning
> On Mar 17, 2016, at 9:15 PM, Eric Smith wrote:
>
> On Thu, Mar 17, 2016 at 3:35 PM, Guy Sotomayor wrote:
>> I’m planning on doing a 4 layer board so I can avoid having routing issues
>> due to 3 different
>> power supply voltages (yea, modern low voltage design meets 5v). I haven’t
>> done
