[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:469 +if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) { + LLVM_DEBUG(dbgs() << "Trying Vemtama custom opcode table:\n"); + Result = decodeInstruction

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D139995/new/ https://reviews.llvm.org/D139995 ___

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

kito-cheng added a comment. Ken has updated spec to clarify requirements of those vector crypto extensions: https://github.com/riscv/riscv-crypto/commit/40695306f628e6dc764d1d0f35392eac792d2c3b These Vector Crypto Extensions can be built on any RISC-V base. However, XLEN=32 implementations

[PATCH] D140361: [RISCV] Merge Masked and unMasked RVV manual codegen

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks for clean up this! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140361/new/ https://reviews.llvm.org/D140361

[PATCH] D140389: [NFC][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'

kito-cheng added a comment. Could you rebase with D140361 ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140389/new/ https://reviews.llvm.org/D140389 ___ cfe-commits ma

[PATCH] D136817: [RISCV] Add H extension

kito-cheng updated this revision to Diff 485360. kito-cheng added a comment. Changes: - Rebase to main - Add negative test. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 Files: clang/test/Preprocesso

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng created this revision. kito-cheng added reviewers: craig.topper, asb, reames. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rog

[PATCH] D140692: [RISCV] Add Svbmpt extension support.

kito-cheng added a comment. You are typo on title and commit log, it should be `Svpbmt` not `Svbmpt`, but the code changes are right, and you need to update `llvm/docs/RISCVUsage.rst` too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140692/new/

[PATCH] D140692: [RISCV] Add Svpbmt extension support.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140692/new/ https://reviews.llvm.org/D140692 ___

[PATCH] D140662: [NFC][Clang][RISCV] Reduce boilerplate when determining prototype for segment loads

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Go ahead, thanks for clean up! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140662/new/ https://reviews.llvm.org/D140662 _

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added a comment. > So if I read this correctly, the effect of this is that we never pass > -target-cpu to the backend after this patch and will only pass > -target-feature and -tune-cpu? Yes, that's prevent us taking any extensions from `-target-cpu`, so always pass `-target-feature

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5457 + // RISC-V will handle -mcpu option in Clang::AddRISCVTargetArgs. + if (!Triple.isRISCV()) { +// Add the target cpu craig.topper wrote: > I wonder if we should stop ge

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 485674. kito-cheng added a comment. Changes: - Stop calling getRISCVTargetCPU in getCPUName. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140693/new/ https://reviews.llvm.org/D140693 Files: clang/lib/Dr

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/lib/Driver/ToolChains/Clang.cpp:5457 + // RISC-V will handle -mcpu option in Clang::AddRISCVTargetArgs. + if (!Triple.isRISCV()) { +// Add the target cpu craig.topper wrote: > kito-cheng wrote: > > craig.t

[PATCH] D136817: [RISCV] Add H extension

kito-cheng added a comment. ping :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D136817/new/ https://reviews.llvm.org/D136817 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.o

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng planned changes to this revision. kito-cheng added a comment. - @craig.topper has suggested we could pass all extension with `-` or `+` to neutralize the effect of the `-target-cpu`, that's less intrusive way. - Add release note to mention the behavior change. Repository: rG LLVM G

[PATCH] D136817: [RISCV] Add H extension

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf4c887c3a840: [RISCV] Add H extension (authored by kito-cheng). Changed prior to commit: https://reviews.llvm.org/D136817?vs=485360&id=487624#toc

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 488173. kito-cheng added a comment. Herald added subscribers: llvm-commits, hiraditya. Herald added a project: LLVM. Changes: - Add release note to mention the behavior change for `-march` and `-mcpu`. - New way to implement this behavior, passing all supp

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng updated this revision to Diff 488175. kito-cheng added a comment. Changes: - Trim unexpected change by clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D140693/new/ https://reviews.llvm.org/D140693 Files: clang/docs/ReleaseN

[PATCH] D140693: [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-cpus.c:13 +// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "+c" +// MCPU-SYNTACORE-SCR1-BASE: "-target-feature" "-64bit" // MCPU-SYNTACORE-SCR1-BASE: "-target-abi" "ilp32" Need to break this in

[PATCH] D139995: [RISCV] Refactor RVV Policy by structure

kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:100 + bool MU = false; + bool MA = false; + bool IntrinsicWithoutMU = false; Maybe use enum value for tail/mask policy? *U and *A are mutually exclusive, so I fee

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

kito-cheng marked 2 inline comments as done. kito-cheng added a comment. @kadircet ooops, sorry for missing your comment, let me figure out how to fix that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124730/new/ https://reviews.llvm.org/D124730

[PATCH] D138287: [clang][RISCV] Drop caching from RVVType as it introduces data races

kito-cheng added a comment. Apparently I missed those comments during llvm dev meeting, I'll figure out a fix soon. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138287/new/ https://reviews.llvm.org/D138287 ___

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

kito-cheng created this revision. kito-cheng added reviewers: ilya-biryukov, kadircet, sammccall, khchen. Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck

[PATCH] D138287: [clang][RISCV] Drop caching from RVVType as it introduces data races

kito-cheng added a comment. Proposed fix: D138429 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138287/new/ https://reviews.llvm.org/D138287 ___ cfe-commits mailing lis

[PATCH] D124730: [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

kito-cheng added a comment. @kadircet Proposed fix: D138429 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124730/new/ https://reviews.llvm.org/D124730 ___ cfe-commits m

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

kito-cheng updated this revision to Diff 477406. kito-cheng added a comment. Changes: - Add comment for RVVTypeCache - computeRVVTypeHashValue become a local function rather than static function of RVVTypeCache. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

kito-cheng marked 3 inline comments as done. kito-cheng added inline comments. Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:284 + +class RVVTypeCache { +private: khchen wrote: > nit: maybe we could add some comments to said the motivation for >

[PATCH] D138429: [clang][RISCV][NFC] Prevent data race in RVVType::computeType

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. kito-cheng marked 2 inline comments as done. Closed by commit rG3fe89be80159: [clang][RISCV][NFC] Prevent data race in RVVType::computeType (authored by kito-cheng). R

[PATCH] D138930: [RISCV] Add macro to imply compiler availability on RISC-V Vector intrinsics version

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM. I am thinking that we should use same way to define both `__riscv_v_intrinsic_overloading`[1] and `__riscv_v_intrinsic`, `__riscv_v_intrinsic_overloading` is defined in `riscv_v

[PATCH] D155674: [RISCV] Update zihintntl to 1p0

kito-cheng added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:149 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izihintntl0p2 -x c -E -dM %s \ +// RUN: -march=rv32izihintntl1p0 -x c -E -dM

[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

kito-cheng added a comment. Does it possible to add a precommit test case to show that we accept unexpected combination of the type? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156223/new/ https://reviews.llvm.org/D156223 __

[PATCH] D156394: [Clang][RISCV] Bump rvv intrinsics version to v0.12

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156394/new/ https://reviews.llvm.org/D156394 ___

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

kito-cheng added inline comments. Comment at: clang/lib/Headers/riscv_ntlh.h:28 + __builtin_riscv_ntl_load((PTR), __RISCV_NTLH_ALL) +#define SELECT_NTL_LOAD(_1, _2, NAME, ...) NAME + `__SELECT_NTL_LOAD` Comment at: clang/lib/Headers/riscv_ntlh

[PATCH] D154050: [Clang][RISCV] Fix RISC-V vector / SiFive intrinsic inclusion in SemaLookup

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks for quick fix! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154050/new/ https://reviews.llvm.org/D154050

[PATCH] D157953: [CGCall][RISCV] Handle function calls with parameter of RVV tuple type

kito-cheng added a comment. Herald added a subscriber: sunshaoce. LGTM, but I would like to wait few more days to make sure no other comment Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D157953/new/ https://reviews.llvm.org/D157953 ___

[PATCH] D155456: [RISCV] Support -m[no-]strict-align options

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/test/Driver/riscv-features.c:41 +// DEFAULT: "-target-feature" "-unaligned-scalar-mem" +// DEFAULT-NOT: "-target-feature" "+unaligned-scalar-me

[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:136 case Invalid: + case Undefined: llvm_unreachable("Unhandled type."); 4vtomat w

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, and the change seems like is fewer than my exception :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156221/new/ https://reviews.

[PATCH] D157663: [Driver] Default riscv*- triples to -fdebug-default-version=4

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, I am OK with that, actually our downstream toolchain has downgrade the dwarf version to 4 too, because binutils/gdb not well support before... Repository: rG LLVM Github Monor

[PATCH] D154171: [RISCV] Mark zvkn* and zvks* extensions as enabled when all their subextensions are.

kito-cheng accepted this revision. kito-cheng added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154171/new/ https://reviews.llvm.org/D154171 ___ cfe-commits mailing list cfe-commits@lis

[PATCH] D152996: [RISCV][POC] Model frm control for vfadd

kito-cheng accepted this revision. kito-cheng added a comment. LGTM, Give my blessing, thanks for moving this forward :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D152996/new/ https://reviews.llvm.org/D152996 ___

[PATCH] D154572: [RISCV] Use 'long' in aes64 Zknd/Zkne builtin tests. NFC

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154572/new/ https://reviews.llvm.org/D154572 ___

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng created this revision. kito-cheng added a reviewer: asb. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng updated this revision to Diff 538094. kito-cheng added a comment. Chagnes: - Update header comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154706/new/ https://reviews.llvm.org/D154706 Files: clang/lib/Headers/CMakeLists.txt

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng updated this revision to Diff 538497. kito-cheng added a comment. Changes: - Define __RISCV_INT_H Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154706/new/ https://reviews.llvm.org/D154706 Files: clang/lib/Headers/CMakeLists.txt cl

[PATCH] D154706: [RISCV] Add XLEN width integer type: riscv_int.h

kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: clang/lib/Headers/riscv_int.h:10 + +#ifndef __RISCV_INT_H + craig.topper wrote: > Don't you have to `#define __RISCV_INT_H` after this to make this a complete > include gu

[PATCH] D118225: [RISCV] Decouple Zve* extensions.

kito-cheng added a comment. Discussion on riscv-v-spec : https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867, although v-spec and isa-spec still not clearly describe that, but seems ISA folks prefer having those implication relationship between those zve* and v extensions.

[PATCH] D119250: [RISCV][NFC] Refactor RISCVISAInfo.

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119250/new/ https://reviews.llvm.org/D119250 ___

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

kito-cheng created this revision. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, abidh, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, j

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added a comment. Herald added a subscriber: achieveartificialintelligence. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 ___ cfe-commits maili

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 378729. kito-cheng added a comment. Changes: - Rebase to main - Remove b and zbproposedc. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clang/include/c

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added inline comments. Comment at: clang/lib/Sema/SemaLookup.cpp:923 + + const RVVIntrinsicInfo *Intrinsic = std::find_if( + std::begin(RVVIntrinsicInfos), std::end(RVVIntrinsicInfos), rogfer01 wrote: > Not for this patch: I think this table may

[PATCH] D112398: [RISCV] Add ABI testing for Float16.

kito-cheng added a comment. Herald added subscribers: VincentWu, luke957. From the psABI aspect, we already included that by this PR , this PR added size and alignment for `_Float16`, and we didn't added extra rule for that, because

[PATCH] D113237: [RISCV] Support I extension version 2.1

kito-cheng added a comment. There is several issue around the default extension version stuffs. - Should we add `-misa-spec=` option to Clang/LLVM? - Behavior for `zifencei` and `zicsr` with `i` 2.0? - How to encode the extension version in LLVM? by attribute or module flags? --- Should we add

[PATCH] D115430: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info

kito-cheng added a comment. Could you re-upload diff with full context? You can create that via `git format-patch -1 -U999` or `git diff -U99 > mypatch.patch`. [1] https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface Repository: rG LLVM Github Monorepo C

[PATCH] D113237: [RISCV] Support I extension version 2.1

kito-cheng added a comment. @jrtc27 > Outside of the I/F/D special cases, where F/D don't really matter and I2p0 is > just I2p1Zicsr2p0_Zifencei2p0,, I thought the new policy was that ratified > extensions would never be changed, only new extensions published, and thus > version numbers are ba

[PATCH] D113237: [RISCV] Support I extension version 2.1

kito-cheng added a comment. @asb > Are you saying that there won't be a new ISA manual release (using whatever > naming scheme) that incorporates the ratified versions of bitmanip, crypto, > vector etc? Oh, I guess I using some word too strong there, here should have some newer release in fut

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

kito-cheng added a comment. Revert due to windows build regression fail: https://lab.llvm.org/buildbot/#/builders/216/builds/195 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119837/new/ https://reviews.llvm.org/D119837 __

[PATCH] D119837: [RISCV] Fix the include search path order between sysroot and resource folder

kito-cheng added a comment. Recommit with windows path fix: https://reviews.llvm.org/rG47b1fa5fc48821eefefd157ed4af2f2cf3bacef4 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D119837/new/ https://reviews.llvm.org/D119837 ___

[PATCH] D120449: [RISCV][RVV] Add strict vfcvt intrinsics that have side effects for dynamically-set rounding mode

kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4683 +Ops.push_back(VL); +Ops.push_back(DAG.getUNDEF(XLenVT)); // Policy + } Is this operand for tail policy? if so why this is `UNDEF`? I guess this should be `TA

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

kito-cheng added inline comments. Comment at: clang/test/Driver/riscv-gnutools.c:19 +// Check default when -mno-relax and -fno-integrated-as specified +// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \ --

[PATCH] D120967: [NFC] Divide tests into smaller files

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Do you mind give more comment on SUMMARY to describe what you did? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D120967/new/ https://rev

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng commandeered this revision. kito-cheng edited reviewers, added: HsiangKai; removed: kito-cheng. kito-cheng added a comment. @HsiangKai hand over this revision to me. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111617/new/ https://revie

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng updated this revision to Diff 400358. kito-cheng added a comment. Herald added subscribers: alextsao1999, hiraditya. Changes: - Using different approach to implement to prevent build time explosion. - build time for `SemaRVVLookup.cpp` is ~6 sec in my machine. Repository: rG LLVM

[PATCH] D111617: [RISCV] Lazily add RVV C intrinsics.

kito-cheng added a comment. TL;DR: -- - Binary size of clang increase ~200k, which is +0.07% for debug build and +0.13% for release build. - Single file compilation speed up ~33x speed up for debug build and ~8.5x speed up for release build - Regression time reduce ~10% (`ninja check-all`,

[PATCH] D103228: [PoC][RISCV] Using pragma to register vector intrinsic

kito-cheng abandoned this revision. kito-cheng added a comment. Herald added subscribers: alextsao1999, VincentWu, luke957, achieveartificialintelligence. Further development move to https://reviews.llvm.org/D111617 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://revi

[PATCH] D117724: [RISCV] Remove Zvlsseg extension.

kito-cheng added a comment. Few more grep result (by `grep zvlsseg * -Rin`), I think should remove: clang/include/clang/Basic/riscv_vector.td:218: // Sub extension of vector spec. Currently only support Zvlsseg. clang/include/clang/Basic/riscv_vector.td:221: // Number of fields for Zvlss

[PATCH] D113336: [RISCV] Imply extensions in RISCVTargetInfo::initFeatureMap

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. Otherwise LGTM. Comment at: clang/lib/Basic/Targets/RISCV.cpp:220 - return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); + unsigned XLen = Featur

[PATCH] D112613: [Clang][RISCV] Change TARGET_BUILTIN to require zve32x for vector instruction

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112613/new/ https://reviews.llvm.org/D112613 ___

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 379329. kito-cheng marked 11 inline comments as done. kito-cheng added a comment. Changes: - Address @craig.topper's comment - Add XLen to constructor of RISCVISAInfo. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llv

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:388 +const std::vector &Features) { + std::unique_ptr ISAInfo(new RISCVISAInfo()); + assert(XLen == 32 || XLen == 64); craig.topper wrote: > Use > > ```

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:39 + +static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn"; + craig.topper wrote: > 'b' shouldn't be in this list anymore? I would prefer to keep that for sync with ISA manual,

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added a comment. Committed with one minor update for version of zba/zbb/zbc/zbs. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 ___ cfe-commits mail

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:39 + +static constexpr StringLiteral AllStdExts = "mafdqlcbjtpvn"; + kito-cheng wrote: > craig.topper wrote: > > 'b' shouldn't be in this list anymore? > I would prefer to keep that f

[PATCH] D111529: Specify Clang vector builtins.

kito-cheng added inline comments. Comment at: clang/docs/LanguageExtensions.rst:579 + NaNs, fmax() return a NaN. + ET __builtin_reduce_add(VT a) \+ integer and floatin

[PATCH] D107290: [PoC][RISCV] Add support for the vscale_range attribute

kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:106 + assert(RVVBitsMin % 128 == 0 && + "RVV requires vector length in multiples of 128!"); + assert(RVVBitsMax % 128 == 0 && RISC-V require VLEN in power of 2, m

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 369364. kito-cheng added a comment. Changes: - Remove unused argument MArch for getExtensionVersion. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clan

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng marked an inline comment as done. kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:268 +// omitted from the version string. E.g., rv32i2p0, rv32i2, rv32i2p1. +static Error getExtensionVersion(StringRef MArch, StringRef Ext, StringRef In,

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 370174. kito-cheng marked an inline comment as done. kito-cheng added a comment. Changes: - Check feature combination is valid. - Change return type of parseFeatures to llvm::Expected>. - Set default extension version in getExtensionVersion. Repository:

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng marked 2 inline comments as done. kito-cheng added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:387 +ExtensionInfoIterator->Version.Minor); + if (ExtName == "e") +HasE = true; Jim wrote: > Does

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 371509. kito-cheng marked 2 inline comments as done. kito-cheng added a comment. Changes: - Address Jim's comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng added a comment. Seems like conflict with D108187 , will update after testing :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 _

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

kito-cheng updated this revision to Diff 372939. kito-cheng added a comment. Changes: - Rebase to `main`. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 Files: clang/include/clang/Basic/DiagnosticComm

[PATCH] D145164: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux

This revision was automatically updated to reflect the committed changes. Closed by commit rGbe437f3bb8b6: [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D145074: [clang][RISCV] Fix ABI lowering for _Float16 for FP ABIs

kito-cheng added a comment. LGTM, just a nit :) Comment at: clang/test/CodeGen/RISCV/riscv64-abi.c:1909 - NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -// LP64F: {{.*}} This seems removed accidentally, I

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

kito-cheng added inline comments. Comment at: clang/lib/Driver/Driver.cpp:4231-4235 + // marchs and quits. + if (Args.getLastArg(options::OPT_print_supported_marchs)) { +RISCVMarchHelp(); +exit(0); + } Plz did the similar action like what OPT_print_sup

[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to S11

kito-cheng added a comment. Sorry for cross post, but I guess some people might not follow closely in discourse (like me :P): Another proposal from me is using gp as platform register: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/371 Some advantage on taking gp as platform registe

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

kito-cheng added a comment. I would support have `-march=help`, but I know it's really not make scene to alias `-march=help` to `--print-supported-extensions` for other targets, what about redirect that in `Driver.cpp` for RISC-V only? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST

[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, let it go Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D149314/new/ https://reviews.llvm.org/D149314

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

This revision was automatically updated to reflect the committed changes. Closed by commit rGda4fcb0c0b28: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple. (authored by kito-cheng). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

kito-cheng accepted this revision. kito-cheng added a comment. I am really happy to see this happen, binutils has relaxed for a while in more relaxed way[1] - only require must start with `rv[32|64][e|i|g]`, personally I would like to relax the order at all like binutils did for GCC, but I don't

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

kito-cheng added inline comments. Comment at: clang/tools/driver/cc1_main.cpp:187-188 +/// Print supported extensions of the given target. +static int PrintSupportedExtensions(std::string TargetStr) { + llvm::riscvMarchHelp(); + Plz make sure only RISC-V print t

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

kito-cheng accepted this revision. kito-cheng added a comment. LGTM, but IMO the title should still contain [RISCV][clang] Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148223/new/ https://reviews.llvm.org/D148223 _

[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM, thanks! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148308/new/ https://reviews.llvm.org/D148308 __

[PATCH] D148680: [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td

kito-cheng accepted this revision. kito-cheng added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148680/new/ https://reviews.llvm.org/D148680 ___

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

kito-cheng accepted this revision. kito-cheng added a comment. LGTM, consider about the GNU compatibility, I would that has -march=help form for that. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.llvm.org/D146054

[PATCH] D146987: [Assignment Tracking] Enable by default

kito-cheng added a comment. Got crash for RISC-V on top of trunk: [kitoc@hsinchu02 build]$ cat x.c typedef __rvv_uint32m4_t a; void b() { a c; } [kitoc@hsinchu02 build]$ bin/clang -target riscv64-elf x.c -O -g clang-14: /home/kitoc/llvm-workspace/llvm-project/llvm/lib/IR/DebugInfo.cpp:

[PATCH] D149642: [RISCV] Support vreinterpret intrinsics between vector boolean type and m1 vector integer type

kito-cheng added inline comments. Comment at: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c:1 -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// NOTE: Assertions have been autogenerated by utils/upd

[PATCH] D146054: [RISCV] Add --print-supported-extensions and -march=help support

kito-cheng added a comment. GCC ins't implement yet, but planed, so add it later I think? @4vtomat already drop -march=help, @MaskRay did you mind take a look again? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D146054/new/ https://reviews.llvm.or

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