This revision was automatically updated to reflect the committed changes.
Closed by commit rG34e055d33e37: [Clang][RISCV] Implement getConstraintRegister
for RISC-V (authored by luismarques).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D108624/new/
asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.
Looks good to me - I'm surprised only Arm, AArch64, and X86 implement this!
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D108624/new/
luismarques added inline comments.
Comment at: clang/test/Sema/inline-asm-validate-riscv.c:27-28
+ register long x10 asm("x10");
+ asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm
clobber list}}
+ asm volatile("" :: "r"(x10) : "a0"); //
luismarques updated this revision to Diff 368323.
luismarques added a comment.
Nit: remove nop.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D108624/new/
https://reviews.llvm.org/D108624
Files:
clang/lib/Basic/Targets/RISCV.h
luismarques created this revision.
luismarques added reviewers: asb, thopre.
Herald added subscribers: vkmr, frasercrmck, evandro, apazos, sameer.abuasal,
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck,
rogfer01, edward-jones, zzheng, jrtc27, shiva0217,
