[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames created this revision. reames added reviewers: craig.topper, asb, frasercrmck, kito-cheng, jrtc27. Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, Mar

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:437 + +// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s Naming wise, is xven

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames updated this revision to Diff 473001. reames added a comment. Fix silly typo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISA

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added inline comments. Comment at: clang/test/Preprocessor/riscv-target-features.c:437 + +// RUN: %clang -target riscv64 -march=rv64ixventanacondops -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s reames wrote:

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added a comment. Do these need their own DecoderNameSpace? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames added a comment. In D137350#3906126 , @craig.topper wrote: > Do these need their own DecoderNameSpace? What is a decoder namespace? Some quick grepping and googling isn't very informative. Comment at: llvm/lib/Target/RISCV/R

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames updated this revision to Diff 473022. reames added a comment. Address review comments from @craig.topper CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added a comment. In D137350#3906234 , @reames wrote: > In D137350#3906126 , @craig.topper > wrote: > >> Do these need their own DecoderNameSpace? > > What is a decoder namespace? Some quick grepping

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

jrtc27 added a comment. In D137350#3906126 , @craig.topper wrote: > Do these need their own DecoderNameSpace? I was going to come here to request that CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames updated this revision to Diff 473272. reames added a comment. Add a decoder namespace. I did one per vendor - i.e. used a Ventana table rather than a VentanaCondOps one. In theory, we could have a vendor who ships incompatible extensions (in two different pieces of hardware), but if we

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames updated this revision to Diff 473285. reames added a comment. Rebase CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

kito-cheng added inline comments. Comment at: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:469 +if (STI.getFeatureBits()[RISCV::FeatureVendorXVentanaCondOps]) { + LLVM_DEBUG(dbgs() << "Trying Vemtama custom opcode table:\n"); + Result = decodeInstruction

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames updated this revision to Diff 474620. reames added a comment. Address Kito's review comments CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td:14 +//===--===// +// -XVentanaCondOps +//===--==

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

reames updated this revision to Diff 474782. reames added a comment. Address comments from @craig.topper CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D137350/new/ https://reviews.llvm.org/D137350 ___ cfe-commits mailing list c

[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG780c53984449: [RISCV] Implement assembler support for XVentanaCondOps (authored by reames). Repository: rG LLVM Github Monorepo CHANGES SINCE LAS