This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2a5661c84158: [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description (authored by asb). Herald added a project: clang. Herald added a subscriber: cfe-commits.
Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148634/new/ https://reviews.llvm.org/D148634 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s Index: llvm/test/MC/RISCV/attribute-arch.s =================================================================== --- llvm/test/MC/RISCV/attribute-arch.s +++ llvm/test/MC/RISCV/attribute-arch.s @@ -234,8 +234,8 @@ .attribute arch, "rv32izifencei2p0" # CHECK: attribute 5, "rv32i2p1_zifencei2p0" -.attribute arch, "rv32izfa0p1" -# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1" +.attribute arch, "rv32izfa0p2" +# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" .attribute arch, "rv32izicond1p0" # CHECK: attribute 5, "rv32i2p1_zicond1p0" Index: llvm/test/CodeGen/RISCV/attributes.ll =================================================================== --- llvm/test/CodeGen/RISCV/attributes.ll +++ llvm/test/CodeGen/RISCV/attributes.ll @@ -193,7 +193,7 @@ ; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0" ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0" ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0" -; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1" +; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" ; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" ; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0" ; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" @@ -264,7 +264,7 @@ ; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0" ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0" ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0" -; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p1" +; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2" ; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" ; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0" ; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -139,7 +139,7 @@ {"zcb", RISCVExtensionVersion{1, 0}}, {"zcd", RISCVExtensionVersion{1, 0}}, {"zcf", RISCVExtensionVersion{1, 0}}, - {"zfa", RISCVExtensionVersion{0, 1}}, + {"zfa", RISCVExtensionVersion{0, 2}}, {"zicond", RISCVExtensionVersion{1, 0}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}}, Index: llvm/docs/ReleaseNotes.rst =================================================================== --- llvm/docs/ReleaseNotes.rst +++ llvm/docs/ReleaseNotes.rst @@ -166,6 +166,7 @@ on RISC-V, but conforms with the new "platform register" defined in the RISC-V psABI (for more details see the `psABI discussion <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370>`_). +* Added support for Zfa extension version 0.2. Changes to the WebAssembly Backend ---------------------------------- Index: llvm/docs/RISCVUsage.rst =================================================================== --- llvm/docs/RISCVUsage.rst +++ llvm/docs/RISCVUsage.rst @@ -188,7 +188,7 @@ LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_. ``experimental-zfa`` - LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25). + LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/zfa-20230414.pdf>`_. ``experimental-zicond`` LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1`>_. Index: clang/test/Preprocessor/riscv-target-features.c =================================================================== --- clang/test/Preprocessor/riscv-target-features.c +++ clang/test/Preprocessor/riscv-target-features.c @@ -518,12 +518,12 @@ // CHECK-ZIFENCEI-EXT: __riscv_zifencei 2000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izfa0p1 -x c -E -dM %s \ +// RUN: -march=rv32izfa0p2 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izfa0p1 -x c -E -dM %s \ +// RUN: -march=rv64izfa0p2 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s -// CHECK-ZFA-EXT: __riscv_zfa 1000{{$}} +// CHECK-ZFA-EXT: __riscv_zfa 2000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zve64x_zvkb0p3 -x c -E -dM %s \
Index: llvm/test/MC/RISCV/attribute-arch.s =================================================================== --- llvm/test/MC/RISCV/attribute-arch.s +++ llvm/test/MC/RISCV/attribute-arch.s @@ -234,8 +234,8 @@ .attribute arch, "rv32izifencei2p0" # CHECK: attribute 5, "rv32i2p1_zifencei2p0" -.attribute arch, "rv32izfa0p1" -# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1" +.attribute arch, "rv32izfa0p2" +# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" .attribute arch, "rv32izicond1p0" # CHECK: attribute 5, "rv32i2p1_zicond1p0" Index: llvm/test/CodeGen/RISCV/attributes.ll =================================================================== --- llvm/test/CodeGen/RISCV/attributes.ll +++ llvm/test/CodeGen/RISCV/attributes.ll @@ -193,7 +193,7 @@ ; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0" ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0" ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0" -; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1" +; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2" ; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" ; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0" ; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" @@ -264,7 +264,7 @@ ; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0" ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0" ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0" -; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p1" +; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2" ; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" ; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0" ; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -139,7 +139,7 @@ {"zcb", RISCVExtensionVersion{1, 0}}, {"zcd", RISCVExtensionVersion{1, 0}}, {"zcf", RISCVExtensionVersion{1, 0}}, - {"zfa", RISCVExtensionVersion{0, 1}}, + {"zfa", RISCVExtensionVersion{0, 2}}, {"zicond", RISCVExtensionVersion{1, 0}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}}, Index: llvm/docs/ReleaseNotes.rst =================================================================== --- llvm/docs/ReleaseNotes.rst +++ llvm/docs/ReleaseNotes.rst @@ -166,6 +166,7 @@ on RISC-V, but conforms with the new "platform register" defined in the RISC-V psABI (for more details see the `psABI discussion <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370>`_). +* Added support for Zfa extension version 0.2. Changes to the WebAssembly Backend ---------------------------------- Index: llvm/docs/RISCVUsage.rst =================================================================== --- llvm/docs/RISCVUsage.rst +++ llvm/docs/RISCVUsage.rst @@ -188,7 +188,7 @@ LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_. ``experimental-zfa`` - LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25). + LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/zfa-20230414.pdf>`_. ``experimental-zicond`` LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1`>_. Index: clang/test/Preprocessor/riscv-target-features.c =================================================================== --- clang/test/Preprocessor/riscv-target-features.c +++ clang/test/Preprocessor/riscv-target-features.c @@ -518,12 +518,12 @@ // CHECK-ZIFENCEI-EXT: __riscv_zifencei 2000000{{$}} // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv32izfa0p1 -x c -E -dM %s \ +// RUN: -march=rv32izfa0p2 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \ -// RUN: -march=rv64izfa0p1 -x c -E -dM %s \ +// RUN: -march=rv64izfa0p2 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFA-EXT %s -// CHECK-ZFA-EXT: __riscv_zfa 1000{{$}} +// CHECK-ZFA-EXT: __riscv_zfa 2000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zve64x_zvkb0p3 -x c -E -dM %s \
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