This revision was automatically updated to reflect the committed changes.
Closed by commit rG71a7108ee91a: [RISCV][MC] MC layer support for xcvmem and
xcvelw extensions (authored by liaolucy).
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craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM
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liaolucy updated this revision to Diff 558107.
liaolucy added a comment.
1. use a custom parser to parse Register-Register load/store
2. Rebase
Thanks
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craig.topper added inline comments.
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2509
// Attempt to parse token as a register.
- if (parseRegister(Operands, true).isSuccess())
+ if (parseRegister(Operands, true).isSuccess()) {
+// Parse memory base
liaolucy added a comment.
ping
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liaolucy updated this revision to Diff 556222.
liaolucy added a comment.
1. Rebase.
2. Update RISCVISAInfoTest.cpp
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liaolucy updated this revision to Diff 553911.
liaolucy added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Address comments from Jim, thanks.
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