https://github.com/SpencerAbson closed
https://github.com/llvm/llvm-project/pull/118115
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https://github.com/SpencerAbson updated
https://github.com/llvm/llvm-project/pull/118115
>From e1181dd6dab09b20be8077d1f4e70ef4da7ab437 Mon Sep 17 00:00:00 2001
From: Spencer Abson
Date: Mon, 25 Nov 2024 21:47:20 +
Subject: [PATCH 1/2] [AArch64] Implement intrinsics for SME FP8 FMOPA
---
https://github.com/CarolineConcatto approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/118115
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@@ -305,6 +305,21 @@ multiclass sme_outer_product_fp32 sz,
ZPRRegOp zpr_ty, string mne
def : SME_ZA_Tile_TwoPred_TwoVec_Pat;
}
+multiclass sme2_fp8_fmopa_za32 {
+def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8,
mnemonic>, SMEPseudo2Instr {
+ bit
@@ -305,6 +305,21 @@ multiclass sme_outer_product_fp32 sz,
ZPRRegOp zpr_ty, string mne
def : SME_ZA_Tile_TwoPred_TwoVec_Pat;
}
+multiclass sme2_fp8_fmopa_za32 {
+def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8,
mnemonic>, SMEPseudo2Instr {
+ bit
@@ -305,6 +305,21 @@ multiclass sme_outer_product_fp32 sz,
ZPRRegOp zpr_ty, string mne
def : SME_ZA_Tile_TwoPred_TwoVec_Pat;
}
+multiclass sme2_fp8_fmopa_za32 {
+def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8,
mnemonic>, SMEPseudo2Instr {
+ bit
https://github.com/CarolineConcatto commented:
Thank you for the patch Spencer.
https://github.com/llvm/llvm-project/pull/118115
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https://github.com/CarolineConcatto edited
https://github.com/llvm/llvm-project/pull/118115
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@@ -305,6 +305,21 @@ multiclass sme_outer_product_fp32 sz,
ZPRRegOp zpr_ty, string mne
def : SME_ZA_Tile_TwoPred_TwoVec_Pat;
}
+multiclass sme2_fp8_fmopa_za32 {
+def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8,
mnemonic>, SMEPseudo2Instr {
+ bit
https://github.com/SpencerAbson deleted
https://github.com/llvm/llvm-project/pull/118115
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https://github.com/SpencerAbson updated
https://github.com/llvm/llvm-project/pull/118115
>From a92b7a9faba65931918e4c3d6763896f1e1eda6b Mon Sep 17 00:00:00 2001
From: Spencer Abson
Date: Mon, 25 Nov 2024 21:47:20 +
Subject: [PATCH] [AArch64] Implement intrinsics for SME FP8 FMOPA
---
clan
@@ -587,7 +587,6 @@ void SVEType::applyTypespec(StringRef TS) {
ElementBitwidth = 16;
SpencerAbson wrote:
This is exactly what my refactoring work will help us avoid - so don't fear!
https://github.com/llvm/llvm-project/pull/118115
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llvmbot wrote:
@llvm/pr-subscribers-clang
Author: None (SpencerAbson)
Changes
This patch implements the following intrinsics:
8-bit floating-point sum of outer products and accumulate.
``` c
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svmopa_za16[_mf8]_m_fpm(uint64_t tile, svbool_t
https://github.com/SpencerAbson created
https://github.com/llvm/llvm-project/pull/118115
This patch implements the following intrinsics:
8-bit floating-point sum of outer products and accumulate.
``` c
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svmopa_za16[_mf8]_m_fpm(uint64_t tile, svb
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