CarolineConcatto wrote:
I believe it is fixed with this patch:
commit 177cbd16663a2ca36d0d7145c3b62f2d756f8f7f (HEAD -> main, origin/main,
origin/HEAD)
Author: Caroline Concatto
Date: Wed Jun 26 12:35:21 2024 +
[Clang][SME2.1] Add REQUIRES: aarch64-registered-target to test
PR#
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `arc-builder` running on
`arc-worker` while building `clang,llvm` at step 6
"test-build-unified-tree-check-all".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/3/builds/624
Here is the relevant piece
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder
`openmp-offload-sles-build-only` running on `rocm-worker-hw-04-sles` while
building `clang,llvm` at step 6 "Add check check-clang".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/140/builds/815
Here i
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder
`llvm-clang-x86_64-sie-ubuntu-fast` running on `sie-linux-worker` while
building `clang,llvm` at step 6 "test-build-unified-tree-check-all".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/144/builds/90
llvm-ci wrote:
LLVM Buildbot has detected a new failure on builder `clang-ve-ninja` running on
`hpce-ve-main` while building `clang,llvm` at step 4 "annotate".
Full details are available at:
https://lab.llvm.org/buildbot/#/builders/12/builds/720
Here is the relevant piece of the build log for
https://github.com/CarolineConcatto closed
https://github.com/llvm/llvm-project/pull/88710
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aemerson wrote:
Reverse ping
https://github.com/llvm/llvm-project/pull/88710
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https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/88710
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https://github.com/aemerson approved this pull request.
LGTM unless others have comments.
https://github.com/llvm/llvm-project/pull/88710
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@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
@@ -674,3 +674,26 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def SVLUTI4_LANE_Z
@@ -2939,59 +2922,18 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr, AArch6
momchil-velikov wrote:
```
if (HasTile) {
MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
MIB.addReg(BaseReg + MI.getOperand(0).getImm());
StartIdx = 1;
} else
MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
}
```
Needs extra braces aro
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr &MI,
- Mac
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88710
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https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88710
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@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr &MI,
- Mac
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr &MI,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr &MI,
- Mac
@@ -2930,17 +2939,59 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr, AArch6
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode
*N, unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs,
Lukacma wrote:
That's a good point. S
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode
*N, unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs,
momchil-velikov wrote:
The real quest
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode
*N, unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs,
Lukacma wrote:
`Scale` could be used
https://github.com/Lukacma deleted
https://github.com/llvm/llvm-project/pull/88710
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@@ -0,0 +1,457 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1 -verify-machineinstrs <
%s | FileCheck %s
+
+;MOVAZ (tile to vector, Multi)
+
+
+;;
+; X2 - Horiz
+;;
+
+d
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
@llvm/pr-subscribers-backend-aarch64
Author: None (CarolineConcatto)
Changes
According to the specification in
ARM-software/acle#309 this adds the intrinsics
// Variants are also available for _za8_u8, _za16_s16, _za16_u16, // _za16_f16,
_za16_
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