[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > > Should we use strings like ARM does so we can get register by name? > > Good point! We may provide two kinds of builtins: one by name, and another by > CSR number. We should continue @lenary's proposal and discuss it in >

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

wangpc-pp wrote: > Should we use strings like ARM does so we can get register by name? Good point! We may provide two kinds of builtins: one by name, and another by CSR number. We should continue @lenary's proposal and discuss it in https://github.com/riscv-non-isa/riscv-toolchain-conventions

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

topperc wrote: Should we use strings like ARM does so we can get register by name? https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

wangpc-pp wrote: GCC gained its `__arm_rsr` and `__arm_wsr` support last year (October, 2023): https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631855.html. So there is no stable released GCC version that supports these builtins. Clang supported these builtins about nine years ago:

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

jrtc27 wrote: I guess my underlying point is that Arm's ACLE provides functions like __arm_rsr, but I'm not aware of them really being used, with inline assembly being the far more common alternative, so what's the real point of providing an interface that developers have already demonstrated

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > You can just use `({ ... })` to achieve that same goal with inline assembly > (and write doesn't even need that, you can do it with a single statement). > I'm not convinced the intrinsics gain you anything. Hmm... I think there's a bit of a disconnect here between the point

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

jrtc27 wrote: You can just use `({ ... })` to achieve that same goal with inline assembly (and write doesn't even need that, you can do it with a single statement). I'm not convinced the intrinsics gain you anything. https://github.com/llvm/llvm-project/pull/85091

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

asb wrote: > In my view, the builtin solution is superior from a usability perspective. I agree, I think Sam's previous work on this stopped due to changing priorities not because there was any real pushback. https://github.com/llvm/llvm-project/pull/85091

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > > > I have always been unconvinced that these are a good idea to have / add > > > significant value over using inline assembly. IIRC Arm has them but > > > nobody uses them? ... > If it’s not a constant integer for inline assembly then how would it > magically be a

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

wangpc-pp wrote: > > > I support adding these builtins personally, but I think we need more > > > discussions on the design. We can achieve the same thing via inline > > > assemblies, that's true. But, from the compiler side, inline assemblies > > > are kind of barriers, we can't do a lot of

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

jrtc27 wrote: > > I support adding these builtins personally, but I think we need more > > discussions on the design. We can achieve the same thing via inline > > assemblies, that's true. But, from the compiler side, inline assemblies are > > kind of barriers, we can't do a lot of

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

topperc wrote: > I support adding these builtins personally, but I think we need more > discussions on the design. We can achieve the same thing via inline > assemblies, that's true. But, from the compiler side, inline assemblies are > kind of barriers, we can't do a lot of

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

wangpc-pp wrote: I support adding these builtins personally, but I think we need more discussions on the design. We can achieve the same thing via inline assemblies, that's true. But, from the compiler side, inline assemblies are kind of barriers, we can't do a lot of

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

jrtc27 wrote: > > I have always been unconvinced that these are a good idea to have / add > > significant value over using inline assembly. IIRC Arm has them but nobody > > uses them? > > Is this a comment about the general concept of builtins to produce specific > instructions or about

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -74,6 +74,21 @@ let TargetPrefix = "riscv" in { } // TargetPrefix = "riscv" +let TargetPrefix = "riscv" in { + // Zicsr + def int_riscv_csrr : +DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem, IntrHasSideEffects, ImmArg>]>;

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -20,6 +20,12 @@ class RISCVBuiltin : TargetBuiltin { let Attributes = [NoThrow, Const] in { //===--===// +// Zicsr extension.

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > I have always been unconvinced that these are a good idea to have / add > significant value over using inline assembly. IIRC Arm has them but nobody > uses them? Is this a comment about the general concept of builtins to produce specific instructions or about these specific

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: > > Individual implementations will provide different sets of CSR's and need a > > way to read/write them. Of course, this can be done with inline asm, but > > doing such things with inline asm has its limitations (no error checking, > > Wouldn't the assembler error check the

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

jrtc27 wrote: I have always been unconvinced that these are a good idea to have / add significant value over using inline assembly. IIRC Arm has them but nobody uses them? https://github.com/llvm/llvm-project/pull/85091 ___ cfe-commits mailing list

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -20,6 +20,12 @@ class RISCVBuiltin : TargetBuiltin { let Attributes = [NoThrow, Const] in { //===--===// +// Zicsr extension.

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

topperc wrote: > Individual implementations will provide different sets of CSR's and need a > way to read/write them. Of course, this can be done with inline asm, but > doing such things with inline asm has its limitations (no error checking, Wouldn't the assembler error check the constant?

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -74,6 +74,21 @@ let TargetPrefix = "riscv" in { } // TargetPrefix = "riscv" +let TargetPrefix = "riscv" in { + // Zicsr + def int_riscv_csrr : +DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], + [IntrNoMem, IntrHasSideEffects, ImmArg>]>;

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

@@ -20,6 +20,12 @@ class RISCVBuiltin : TargetBuiltin { let Attributes = [NoThrow, Const] in { //===--===// +// Zicsr extension.

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

nemanjai wrote: Individual implementations will provide different sets of CSR's and need a way to read/write them. Of course, this can be done with inline asm, but doing such things with inline asm has its limitations (no error checking, if a user attempts to wrap the asm in a function, they

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

llvmbot wrote: @llvm/pr-subscribers-clang-codegen @llvm/pr-subscribers-clang Author: Nemanja Ivanovic (nemanjai) Changes To facilitate proper range checking and better error messages if an attempt is made to call these with non-litaral arguments, we provide builtins to emit the

[clang] [llvm] [RISC-V] Add CSR read/write builtins (PR #85091)

https://github.com/nemanjai created https://github.com/llvm/llvm-project/pull/85091 To facilitate proper range checking and better error messages if an attempt is made to call these with non-litaral arguments, we provide builtins to emit the read/write CSR instructions. >From