https://github.com/jroelofs updated
https://github.com/llvm/llvm-project/pull/96249
>From ee1389a36aac9eecf00513d98cc99787b2cfe17a Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roel...@apple.com>
Date: Thu, 20 Jun 2024 16:26:45 -0700
Subject: [PATCH 1/3] [llvm][AArch64][TableGen] Create a ProcessorAlias record.
NFC
... and use it to organize all of the Apple CPU aliases.
---
llvm/lib/Target/AArch64/AArch64Processors.td | 35 +++++++++-----------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 25 ++++++++++++--
2 files changed, 38 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index 53b46ff42b72f..46f665cb15a9a 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -930,6 +930,12 @@ def ProcessorFeatures {
list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
}
+// Define an alternative name for a given Processor.
+class ProcessorAlias<string n, string alias> {
+ string Name = n;
+ string Alias = alias;
+}
+
// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
// optimizations.
def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
@@ -1050,15 +1056,12 @@ def : ProcessorModel<"tsv110", TSV110Model,
ProcessorFeatures.TSV110,
// Apple CPUs
-// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
-def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
[TuneAppleA7]>;
-def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
-def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
+// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
+def : ProcessorAlias<"cyclone", "apple-a7">;
+def : ProcessorAlias<"apple-a8", "apple-a7">;
+def : ProcessorAlias<"apple-a9", "apple-a7">;
def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
[TuneAppleA10]>;
@@ -1068,28 +1071,23 @@ def : ProcessorModel<"apple-a11", CycloneModel,
ProcessorFeatures.AppleA11,
def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
[TuneAppleA12]>;
-def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
- [TuneAppleA12]>;
-def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
- [TuneAppleA12]>;
+def : ProcessorAlias<"apple-s4", "apple-a12">;
+def : ProcessorAlias<"apple-s5", "apple-a12">;
def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
[TuneAppleA13]>;
def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
[TuneAppleA14]>;
-def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
- [TuneAppleA14]>;
+def : ProcessorAlias<"apple-m1", "apple-a14">;
def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15,
[TuneAppleA15]>;
-def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15,
- [TuneAppleA15]>;
+def : ProcessorAlias<"apple-m2", "apple-a15">;
def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
[TuneAppleA16]>;
-def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16,
- [TuneAppleA16]>;
+def : ProcessorAlias<"apple-m3", "apple-a16">;
def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
[TuneAppleA17]>;
@@ -1098,8 +1096,7 @@ def : ProcessorModel<"apple-m4", CycloneModel,
ProcessorFeatures.AppleM4,
[TuneAppleM4]>;
// Alias for the latest Apple processor model supported by LLVM.
-def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleM4,
- [TuneAppleM4]>;
+def : ProcessorAlias<"apple-latest", "apple-m4">;
// Fujitsu A64FX
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index e22f353b451f9..3e111813280a3 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -221,8 +221,28 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
OS << "#ifdef EMIT_CPU_INFO\n"
<< "inline constexpr CpuInfo CpuInfos[] = {\n";
+ std::map<std::string, std::pair<std::string, const Record *>>
ProcessorModels;
for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorModel")) {
auto Name = Rec->getValueAsString("Name");
+ ProcessorModels.insert(std::make_pair(Name, std::make_pair(Name, Rec)));
+ }
+
+ for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorAlias")) {
+ std::string Name = Rec->getValueAsString("Name").str();
+ auto Alias = Rec->getValueAsString("Alias");
+ auto It = ProcessorModels.find(Alias.str());
+ if (!ProcessorModels
+ .insert(
+ std::make_pair(Name, std::make_pair(Alias,
It->second.second)))
+ .second)
+ PrintFatalError(
+ Rec, "Alias duplicates an existing ProcessorAlias or
ProcessorModel");
+ }
+
+ for (auto &[K, V] : ProcessorModels) {
+ auto Name = K;
+ auto Alias = V.first;
+ auto *Rec = V.second;
auto Features = Rec->getValueAsListOfDefs("Features");
// "apple-latest" is backend-only, should not be accepted by TargetParser.
@@ -253,9 +273,8 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
- // The apple-latest alias is backend only, do not expose it to -mcpu.
- if (Name == "apple-latest")
- continue;
+ if (Name != Alias)
+ OS << " // Alias: " << Name << " -> " << Alias << "\n";
OS << " {\n"
<< " \"" << Name << "\",\n"
>From 5d2fce1d713ca525b3ea338c2ea3c17833d463ec Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roel...@apple.com>
Date: Fri, 21 Jun 2024 09:04:12 -0700
Subject: [PATCH 2/3] Revert "[llvm][AArch64][TableGen] Create a ProcessorAlias
record. NFC"
This reverts commit ee1389a36aac9eecf00513d98cc99787b2cfe17a.
---
llvm/lib/Target/AArch64/AArch64Processors.td | 35 +++++++++++---------
llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 25 ++------------
2 files changed, 22 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index 46f665cb15a9a..53b46ff42b72f 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -930,12 +930,6 @@ def ProcessorFeatures {
list<SubtargetFeature> Generic = [FeatureFPARMv8, FeatureNEON, FeatureETE];
}
-// Define an alternative name for a given Processor.
-class ProcessorAlias<string n, string alias> {
- string Name = n;
- string Alias = alias;
-}
-
// FeatureFuseAdrpAdd is enabled under Generic to allow linker merging
// optimizations.
def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
@@ -1056,12 +1050,15 @@ def : ProcessorModel<"tsv110", TSV110Model,
ProcessorFeatures.TSV110,
// Apple CPUs
+// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
+def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
+ [TuneAppleA7]>;
def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
[TuneAppleA7]>;
-// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
-def : ProcessorAlias<"cyclone", "apple-a7">;
-def : ProcessorAlias<"apple-a8", "apple-a7">;
-def : ProcessorAlias<"apple-a9", "apple-a7">;
+def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
+ [TuneAppleA7]>;
+def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
+ [TuneAppleA7]>;
def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
[TuneAppleA10]>;
@@ -1071,23 +1068,28 @@ def : ProcessorModel<"apple-a11", CycloneModel,
ProcessorFeatures.AppleA11,
def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
[TuneAppleA12]>;
-def : ProcessorAlias<"apple-s4", "apple-a12">;
-def : ProcessorAlias<"apple-s5", "apple-a12">;
+def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
+ [TuneAppleA12]>;
+def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
+ [TuneAppleA12]>;
def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
[TuneAppleA13]>;
def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
[TuneAppleA14]>;
-def : ProcessorAlias<"apple-m1", "apple-a14">;
+def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
+ [TuneAppleA14]>;
def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15,
[TuneAppleA15]>;
-def : ProcessorAlias<"apple-m2", "apple-a15">;
+def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15,
+ [TuneAppleA15]>;
def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
[TuneAppleA16]>;
-def : ProcessorAlias<"apple-m3", "apple-a16">;
+def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16,
+ [TuneAppleA16]>;
def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
[TuneAppleA17]>;
@@ -1096,7 +1098,8 @@ def : ProcessorModel<"apple-m4", CycloneModel,
ProcessorFeatures.AppleM4,
[TuneAppleM4]>;
// Alias for the latest Apple processor model supported by LLVM.
-def : ProcessorAlias<"apple-latest", "apple-m4">;
+def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleM4,
+ [TuneAppleM4]>;
// Fujitsu A64FX
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 3e111813280a3..e22f353b451f9 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -221,28 +221,8 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
OS << "#ifdef EMIT_CPU_INFO\n"
<< "inline constexpr CpuInfo CpuInfos[] = {\n";
- std::map<std::string, std::pair<std::string, const Record *>>
ProcessorModels;
for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorModel")) {
auto Name = Rec->getValueAsString("Name");
- ProcessorModels.insert(std::make_pair(Name, std::make_pair(Name, Rec)));
- }
-
- for (const Record *Rec : RK.getAllDerivedDefinitions("ProcessorAlias")) {
- std::string Name = Rec->getValueAsString("Name").str();
- auto Alias = Rec->getValueAsString("Alias");
- auto It = ProcessorModels.find(Alias.str());
- if (!ProcessorModels
- .insert(
- std::make_pair(Name, std::make_pair(Alias,
It->second.second)))
- .second)
- PrintFatalError(
- Rec, "Alias duplicates an existing ProcessorAlias or
ProcessorModel");
- }
-
- for (auto &[K, V] : ProcessorModels) {
- auto Name = K;
- auto Alias = V.first;
- auto *Rec = V.second;
auto Features = Rec->getValueAsListOfDefs("Features");
// "apple-latest" is backend-only, should not be accepted by TargetParser.
@@ -273,8 +253,9 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
- if (Name != Alias)
- OS << " // Alias: " << Name << " -> " << Alias << "\n";
+ // The apple-latest alias is backend only, do not expose it to -mcpu.
+ if (Name == "apple-latest")
+ continue;
OS << " {\n"
<< " \"" << Name << "\",\n"
>From 7adcf8ebcf48af2cc3271d97b895e711d5e5e102 Mon Sep 17 00:00:00 2001
From: Jon Roelofs <jonathan_roel...@apple.com>
Date: Fri, 21 Jun 2024 12:33:20 -0700
Subject: [PATCH 3/3] use CpuAlias table instead
---
clang/test/Driver/aarch64-mac-cpus.c | 2 +-
clang/test/Misc/target-invalid-cpu-note.c | 4 +--
llvm/include/llvm/MC/MCSubtargetInfo.h | 2 +-
.../llvm/TargetParser/AArch64TargetParser.h | 17 ++++++++++--
llvm/lib/Target/AArch64/AArch64Processors.td | 21 ---------------
.../MCTargetDesc/AArch64MCTargetDesc.cpp | 3 +++
llvm/lib/TargetParser/AArch64TargetParser.cpp | 8 ++++--
llvm/utils/TableGen/SubtargetEmitter.cpp | 26 +++++++++++++++++--
8 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/clang/test/Driver/aarch64-mac-cpus.c
b/clang/test/Driver/aarch64-mac-cpus.c
index 488298cfd2d24..8d23ad8c956fd 100644
--- a/clang/test/Driver/aarch64-mac-cpus.c
+++ b/clang/test/Driver/aarch64-mac-cpus.c
@@ -21,4 +21,4 @@
// EXPLICIT-A11: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a11"
// EXPLICIT-A7: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a7"
// EXPLICIT-A14: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a14"
-// EXPLICIT-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-m1"
+// EXPLICIT-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "apple-a14"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c
b/clang/test/Misc/target-invalid-cpu-note.c
index 59d3aaa122dbe..b69b7a48cf7b5 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
-// AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35,
cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae,
cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75,
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c,
cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82,
cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4,
cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3,
neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae,
exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88,
thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone,
apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4,
apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16,
apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b,
oryon-1, cobalt-100, grace{{$}}
+// AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1, ampere1a,
ampere1b, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15,
apple-a16, apple-a17, apple-a7, apple-a8, apple-a9, apple-m1, apple-m2,
apple-m3, apple-m4, apple-s4, apple-s5, carmel, cobalt-100, cortex-a34,
cortex-a35, cortex-a510, cortex-a520, cortex-a520ae, cortex-a53, cortex-a55,
cortex-a57, cortex-a65, cortex-a65ae, cortex-a710, cortex-a715, cortex-a72,
cortex-a720, cortex-a720ae, cortex-a725, cortex-a73, cortex-a75, cortex-a76,
cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-r82,
cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4,
cortex-x925, cyclone, exynos-m3, exynos-m4, exynos-m5, falkor, generic, grace,
kryo, neoverse-512tvb, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3,
neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, oryon-1, saphira,
thunderx, thunderx2t99, thunderx3t110, thunderxt81, thunderxt83, thunderxt88,
tsv110{{$}}
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
-// TUNE_AARCH64-NEXT: note: valid target CPU values are: generic, cortex-a35,
cortex-a34, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae,
cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75,
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c,
cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-a725, cortex-r82,
cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4,
cortex-x925, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3,
neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae,
exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx, thunderxt88,
thunderxt81, thunderxt83, thunderx2t99, thunderx3t110, tsv110, cyclone,
apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-s4,
apple-s5, apple-a13, apple-a14, apple-m1, apple-a15, apple-m2, apple-a16,
apple-m3, apple-a17, apple-m4, a64fx, carmel, ampere1, ampere1a, ampere1b,
oryon-1, cobalt-100, grace{{$}}
+// TUNE_AARCH64-NEXT: note: valid target CPU values are: a64fx, ampere1,
ampere1a, ampere1b, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14,
apple-a15, apple-a16, apple-a17, apple-a7, apple-a8, apple-a9, apple-m1,
apple-m2, apple-m3, apple-m4, apple-s4, apple-s5, carmel, cobalt-100,
cortex-a34, cortex-a35, cortex-a510, cortex-a520, cortex-a520ae, cortex-a53,
cortex-a55, cortex-a57, cortex-a65, cortex-a65ae, cortex-a710, cortex-a715,
cortex-a72, cortex-a720, cortex-a720ae, cortex-a725, cortex-a73, cortex-a75,
cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c,
cortex-r82, cortex-r82ae, cortex-x1, cortex-x1c, cortex-x2, cortex-x3,
cortex-x4, cortex-x925, cyclone, exynos-m3, exynos-m4, exynos-m5, falkor,
generic, grace, kryo, neoverse-512tvb, neoverse-e1, neoverse-n1, neoverse-n2,
neoverse-n3, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, oryon-1,
saphira, thunderx, thunderx2t99, thunderx3t110, thunderxt81, thunderxt83,
thunderxt88, tsv110{{$}}
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix X86
// X86: error: unknown target CPU 'not-a-cpu'
diff --git a/llvm/include/llvm/MC/MCSubtargetInfo.h
b/llvm/include/llvm/MC/MCSubtargetInfo.h
index ff76435d60843..96897dc76a50c 100644
--- a/llvm/include/llvm/MC/MCSubtargetInfo.h
+++ b/llvm/include/llvm/MC/MCSubtargetInfo.h
@@ -225,7 +225,7 @@ class MCSubtargetInfo {
}
/// Check whether the CPU string is valid.
- bool isCPUStringValid(StringRef CPU) const {
+ virtual bool isCPUStringValid(StringRef CPU) const {
auto Found = llvm::lower_bound(ProcDesc, CPU);
return Found != ProcDesc.end() && StringRef(Found->Key) == CPU;
}
diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
index a40bca9563cdd..7ebe24363be1b 100644
--- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h
+++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h
@@ -304,8 +304,21 @@ struct Alias {
StringRef Name;
};
-inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"},
- {"grace", "neoverse-v2"}};
+inline constexpr Alias CpuAliases[] = {
+ {"cobalt-100", "neoverse-n2"},
+ {"grace", "neoverse-v2"},
+ // Support cyclone as an alias for apple-a7 so we can still LTO old
bitcode.
+ {"cyclone", "apple-a7"},
+ {"apple-a8", "apple-a7"},
+ {"apple-a9", "apple-a7"},
+ {"apple-s4", "apple-a12"},
+ {"apple-s5", "apple-a12"},
+ {"apple-m1", "apple-a14"},
+ {"apple-m2", "apple-a15"},
+ {"apple-m3", "apple-a16"},
+ // Alias for the latest Apple processor model supported by LLVM.
+ {"apple-latest", "apple-m4"},
+};
const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID));
diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td
b/llvm/lib/Target/AArch64/AArch64Processors.td
index 53b46ff42b72f..aa89bdc9a8ace 100644
--- a/llvm/lib/Target/AArch64/AArch64Processors.td
+++ b/llvm/lib/Target/AArch64/AArch64Processors.td
@@ -1050,15 +1050,8 @@ def : ProcessorModel<"tsv110", TSV110Model,
ProcessorFeatures.TSV110,
// Apple CPUs
-// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
-def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
def : ProcessorModel<"apple-a7", CycloneModel, ProcessorFeatures.AppleA7,
[TuneAppleA7]>;
-def : ProcessorModel<"apple-a8", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
-def : ProcessorModel<"apple-a9", CycloneModel, ProcessorFeatures.AppleA7,
- [TuneAppleA7]>;
def : ProcessorModel<"apple-a10", CycloneModel, ProcessorFeatures.AppleA10,
[TuneAppleA10]>;
@@ -1068,28 +1061,18 @@ def : ProcessorModel<"apple-a11", CycloneModel,
ProcessorFeatures.AppleA11,
def : ProcessorModel<"apple-a12", CycloneModel, ProcessorFeatures.AppleA12,
[TuneAppleA12]>;
-def : ProcessorModel<"apple-s4", CycloneModel, ProcessorFeatures.AppleA12,
- [TuneAppleA12]>;
-def : ProcessorModel<"apple-s5", CycloneModel, ProcessorFeatures.AppleA12,
- [TuneAppleA12]>;
def : ProcessorModel<"apple-a13", CycloneModel, ProcessorFeatures.AppleA13,
[TuneAppleA13]>;
def : ProcessorModel<"apple-a14", CycloneModel, ProcessorFeatures.AppleA14,
[TuneAppleA14]>;
-def : ProcessorModel<"apple-m1", CycloneModel, ProcessorFeatures.AppleA14,
- [TuneAppleA14]>;
def : ProcessorModel<"apple-a15", CycloneModel, ProcessorFeatures.AppleA15,
[TuneAppleA15]>;
-def : ProcessorModel<"apple-m2", CycloneModel, ProcessorFeatures.AppleA15,
- [TuneAppleA15]>;
def : ProcessorModel<"apple-a16", CycloneModel, ProcessorFeatures.AppleA16,
[TuneAppleA16]>;
-def : ProcessorModel<"apple-m3", CycloneModel, ProcessorFeatures.AppleA16,
- [TuneAppleA16]>;
def : ProcessorModel<"apple-a17", CycloneModel, ProcessorFeatures.AppleA17,
[TuneAppleA17]>;
@@ -1097,10 +1080,6 @@ def : ProcessorModel<"apple-a17", CycloneModel,
ProcessorFeatures.AppleA17,
def : ProcessorModel<"apple-m4", CycloneModel, ProcessorFeatures.AppleM4,
[TuneAppleM4]>;
-// Alias for the latest Apple processor model supported by LLVM.
-def : ProcessorModel<"apple-latest", CycloneModel, ProcessorFeatures.AppleM4,
- [TuneAppleM4]>;
-
// Fujitsu A64FX
def : ProcessorModel<"a64fx", A64FXModel, ProcessorFeatures.A64FX,
diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
index 6493a2ee4a938..f05e5e6df7f8e 100644
--- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
+++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
@@ -29,6 +29,7 @@
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Endian.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/TargetParser/AArch64TargetParser.h"
using namespace llvm;
@@ -51,6 +52,8 @@ static MCInstrInfo *createAArch64MCInstrInfo() {
static MCSubtargetInfo *
createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+ CPU = AArch64::resolveCPUAlias(CPU);
+
if (CPU.empty()) {
CPU = "generic";
if (FS.empty())
diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp
b/llvm/lib/TargetParser/AArch64TargetParser.cpp
index 7986f07538df7..5311c2c992544 100644
--- a/llvm/lib/TargetParser/AArch64TargetParser.cpp
+++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp
@@ -88,10 +88,14 @@ StringRef AArch64::getArchExtFeature(StringRef ArchExt) {
void AArch64::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
for (const auto &C : CpuInfos)
- Values.push_back(C.Name);
+ Values.push_back(C.Name);
for (const auto &Alias : CpuAliases)
- Values.push_back(Alias.AltName);
+ // The apple-latest alias is backend only, do not expose it to clang's
-mcpu.
+ if (Alias.AltName != "apple-latest")
+ Values.push_back(Alias.AltName);
+
+ llvm::sort(Values);
}
bool AArch64::isX18ReservedByDefault(const Triple &TT) {
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp
b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 60a0402103ce0..1adefea5b0359 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -239,6 +239,9 @@ void
SubtargetEmitter::EmitSubtargetInfoMacroCalls(raw_ostream &OS) {
OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n";
+
+ if (Target == "AArch64")
+ OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
}
//
@@ -1895,6 +1898,10 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream
&OS) {
return;
}
+ if (Target == "AArch64")
+ OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
+ << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
+
OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"
<< " const FeatureBitset &Bits = getFeatureBits();\n";
@@ -1946,6 +1953,11 @@ void
SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
OS << " unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
"override;\n";
}
+ if (Target == "AArch64")
+ OS << " bool isCPUStringValid(StringRef CPU) const override {\n"
+ << " CPU = AArch64::resolveCPUAlias(CPU);\n"
+ << " return MCSubtargetInfo::isCPUStringValid(CPU);\n"
+ << " }\n";
OS << "};\n";
EmitHwModeCheck(Target + "GenMCSubtargetInfo", OS);
}
@@ -2013,6 +2025,9 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "\nstatic inline MCSubtargetInfo *create" << Target
<< "MCSubtargetInfoImpl("
<< "const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
{\n";
+ if (Target == "AArch64")
+ OS << " CPU = AArch64::resolveCPUAlias(CPU);\n"
+ << " TuneCPU = AArch64::resolveCPUAlias(TuneCPU);\n";
OS << " return new " << Target
<< "GenMCSubtargetInfo(TT, CPU, TuneCPU, FS, ";
if (NumFeatures)
@@ -2045,6 +2060,8 @@ void SubtargetEmitter::run(raw_ostream &OS) {
OS << "#include \"llvm/Support/Debug.h\"\n";
OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
+ if (Target == "AArch64")
+ OS << "#include \"llvm/TargetParser/AArch64TargetParser.h\"\n\n";
ParseFeaturesFunction(OS);
OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
@@ -2112,8 +2129,13 @@ void SubtargetEmitter::run(raw_ostream &OS) {
}
OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, "
- << "StringRef TuneCPU, StringRef FS)\n"
- << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
+ << "StringRef TuneCPU, StringRef FS)\n";
+
+ if (Target == "AArch64")
+ OS << " : TargetSubtargetInfo(TT, AArch64::resolveCPUAlias(CPU),\n"
+ << " AArch64::resolveCPUAlias(TuneCPU), FS, ";
+ else
+ OS << " : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ";
if (NumFeatures)
OS << "ArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
else
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