efriedma-quic wrote:
I guess the clang calling convention code never uses MMX types for
passing/returning values?
Have you looked at the code quality? #41665 mentions potential issues with
widening vectors.
This doesn't touch inline asm or _mm_empty; I guess you're leaving that for a
follow
@@ -614,12 +623,15 @@ _mm_shuffle_epi8(__m128i __a, __m128i __b)
///1: Clear the corresponding byte in the destination. \n
///0: Copy the selected source byte to the corresponding byte in the
///destination. \n
-///Bits [3:0] select the source byte to be copied.
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
RKSimon wrote:
Add a deprecation message if SSE2 is not defined or j
https://github.com/jyknight edited
https://github.com/llvm/llvm-project/pull/96540
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@@ -150,8 +150,8 @@ TARGET_BUILTIN(__builtin_ia32_pmovmskb, "iV8c", "ncV:64:",
"mmx,sse")
TARGET_BUILTIN(__builtin_ia32_pmulhuw, "V4sV4sV4s", "ncV:64:", "mmx,sse")
TARGET_BUILTIN(__builtin_ia32_psadbw, "V4sV8cV8c", "ncV:64:", "mmx,sse")
TARGET_BUILTIN(__builtin_ia32_pshufw, "V
https://github.com/jyknight commented:
Thanks for the detailed review comments!
https://github.com/llvm/llvm-project/pull/96540
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@@ -1035,10 +1077,11 @@ _mm_srli_pi32(__m64 __m, int __count)
/// \param __count
///A 64-bit integer vector interpreted as a single 64-bit integer.
/// \returns A 64-bit integer vector containing the right-shifted value.
-static __inline__ __m64 __DEFAULT_FN_ATTRS
+static _
@@ -2108,9 +2106,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_add_epi32(__m128i __a,
/// \param __b
///A 64-bit integer.
/// \returns A 64-bit integer containing the sum of both parameters.
-static __inline__ __m64 __DEFAULT_FN_ATTRS_MMX _mm_add_si64(__m64 __a,
-
@@ -2502,10 +2509,25 @@ _mm_mulhi_pu16(__m64 __a, __m64 __b)
///A pointer to a 64-bit memory location that will receive the
conditionally
///copied integer values. The address of the memory location does not have
///to be aligned.
-static __inline__ void __DEFAULT_
@@ -124,10 +143,11 @@ _mm_cvtm64_si64(__m64 __m)
///written to the upper 32 bits of the result.
/// \returns A 64-bit integer vector of [8 x i8] containing the converted
///values.
-static __inline__ __m64 __DEFAULT_FN_ATTRS
+static __inline__ __m64 __DEFAULT_FN_ATTRS_S
@@ -0,0 +1,29 @@
+USE_XMM=
jyknight wrote:
These are the tests I used to validate that the re-implementation works
properly: I found it extremely important to have validation that my
implementation works properly, because i certainly messed up a few times.
I d
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -1558,10 +1559,10 @@ _mm_cvttss_si64(__m128 __a)
/// \param __a
///A 128-bit vector of [4 x float].
/// \returns A 64-bit integer vector containing the converted values.
-static __inline__ __m64 __DEFAULT_FN_ATTRS_MMX
+static __inline__ __m64 __DEFAULT_FN_ATTRS_SSE2
_mm
@@ -17,13 +17,11 @@
#include
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS
\
- __attribute__((__always_inline__, __nodebug__,
\
-
@@ -0,0 +1,29 @@
+USE_XMM=
+#USE_XMM=--use-xmm
jyknight wrote:
It works if you first delete/ifdef-out test_stores and test_maskmove. I didn't
make those generic.
(The "USE_XMM" version is to validate that the unused bits of the input xmm
registers being set to
@@ -32,12 +32,13 @@ typedef unsigned int __v4su
__attribute__((__vector_size__(16)));
#endif
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS
\
- __attribute__((__always_inlin
@@ -242,10 +243,11 @@ _mm_hadd_epi32(__m128i __a, __m128i __b)
///destination.
/// \returns A 64-bit vector of [4 x i16] containing the horizontal sums of
both
///operands.
-static __inline__ __m64 __DEFAULT_FN_ATTRS_MMX
+static __inline__ __m64 __DEFAULT_FN_ATTRS
_mm
@@ -614,12 +623,15 @@ _mm_shuffle_epi8(__m128i __a, __m128i __b)
///1: Clear the corresponding byte in the destination. \n
///0: Copy the selected source byte to the corresponding byte in the
///destination. \n
-///Bits [3:0] select the source byte to be copied.
@@ -177,7 +175,10 @@ _mm_abs_epi32(__m128i __a)
/// \returns A 64-bit integer vector containing the concatenated right-shifted
///value.
#define _mm_alignr_pi8(a, b, n) \
- ((__m64)__builtin_ia32_palignr((__v8qi)(__m64)(a), (__v8qi)(__m64)(b), (n)))
+ ((__m64)__builtin_sh
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
jyknight wrote:
IIUC, these files intentionally don't have any depen
https://github.com/jyknight edited
https://github.com/llvm/llvm-project/pull/96540
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jyknight wrote:
> I guess the clang calling convention code never uses MMX types for
> passing/returning values?
Correct, Clang never uses MMX types in its calling convention. This is actually
_wrong_ for the 32-bit x86 psABI. You're supposed to pass the first 3 MMX args
in mm0-2, and return
efriedma-quic wrote:
> Or, if we do need to preserve bitcode compat, how to best achieve it? Perhaps
> we convert them into inline-asm in the bitcode upgrader?
Really, the question is whether we plan to completely drop support for the
x86_mmx type (including inline asm operands/results). If w
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -0,0 +1,29 @@
+USE_XMM=
phoebewang wrote:
How about we move these old implementations in to a seperate file (or leave
them where they are if you like) and rename them to _dept, so that we don't
rely on old compilers? We can then remove them as well as th
jyknight wrote:
> Really, the question is whether we plan to completely drop support for the
> x86_mmx type (including inline asm operands/results)
Yes, I do think it would be good to eliminate the type.
For inline-asm, we could switch to using a standard IR vector type for "y"
constraint ope
jyknight wrote:
I believe all the comments here are addressed; any more concerns/comments, or
is this good to go?
https://github.com/llvm/llvm-project/pull/96540
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https://github.com/RKSimon edited
https://github.com/llvm/llvm-project/pull/96540
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https://github.com/RKSimon approved this pull request.
LGTM with a couple of minors
https://github.com/llvm/llvm-project/pull/96540
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@@ -159,6 +159,20 @@ AMDGPU Support
X86 Support
^^^
+- The MMX vector intrinsic functions from ``*mmintrin.h`` which
+ operate on `__m64` vectors, such as ``_mm_add_pi8``, have been
+ reimplemented to use the SSE2 instruction-set and XMM registers
+ unconditionally.
@@ -49,12 +49,10 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16),
__aligned__(16)));
#endif
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS
\
- __attribute__((_
@@ -49,12 +49,10 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16),
__aligned__(16)));
#endif
/* Define the default attributes for the functions in this file. */
-#define __DEFAULT_FN_ATTRS
\
- __attribute__((_
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@@ -159,6 +159,20 @@ AMDGPU Support
X86 Support
^^^
+- The MMX vector intrinsic functions from ``*mmintrin.h`` which
+ operate on `__m64` vectors, such as ``_mm_add_pi8``, have been
+ reimplemented to use the SSE2 instruction-set and XMM registers
+ unconditionally.
@@ -159,6 +159,20 @@ AMDGPU Support
X86 Support
^^^
+- The MMX vector intrinsic functions from ``*mmintrin.h`` which
+ operate on `__m64` vectors, such as ``_mm_add_pi8``, have been
+ reimplemented to use the SSE2 instruction-set and XMM registers
+ unconditionally.
https://github.com/jyknight edited
https://github.com/llvm/llvm-project/pull/96540
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https://github.com/phoebewang approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/96540
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llvmbot wrote:
@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-clang
Author: James Y Knight (jyknight)
Changes
The MMX instruction set is legacy, and the SSE2 variants are in every way
superior, when they are available -- and they have been available since the
Pentium 4 was release
llvmbot wrote:
@llvm/pr-subscribers-llvm-ir
Author: James Y Knight (jyknight)
Changes
The MMX instruction set is legacy, and the SSE2 variants are in every way
superior, when they are available -- and they have been available since the
Pentium 4 was released, 20 years ago.
Therefore, we
github-actions[bot] wrote:
:warning: Python code formatter, darker found issues in your code. :warning:
You can test this locally with the following command:
``bash
darker --check --diff -r
af6acd7442646fde56de919964bd52d7bb7922b2...a17a0df1c3551693283dd806b901d3020f33e67f
mmx-t
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff af6acd7442646fde56de919964bd52d7bb7922b2
a17a0df1c3551693283dd806b901d3020f33e67f --e
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -2539,9 +2536,8 @@ static __inline__ __m128i __DEFAULT_FN_ATTRS
_mm_sub_epi32(__m128i __a,
///A 64-bit integer vector containing the subtrahend.
/// \returns A 64-bit integer vector containing the difference of the values in
///the operands.
-static __inline__ __m64
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -337,10 +363,10 @@ _mm_unpacklo_pi32(__m64 __m1, __m64 __m2)
///A 64-bit integer vector of [8 x i8].
/// \returns A 64-bit integer vector of [8 x i8] containing the sums of both
///parameters.
-static __inline__ __m64 __DEFAULT_FN_ATTRS
+static __inline__ __m64 __DEF
@@ -242,10 +243,11 @@ _mm_hadd_epi32(__m128i __a, __m128i __b)
///destination.
/// \returns A 64-bit vector of [4 x i16] containing the horizontal sums of
both
///operands.
-static __inline__ __m64 __DEFAULT_FN_ATTRS_MMX
+static __inline__ __m64 __DEFAULT_FN_ATTRS
_mm
@@ -1035,10 +1077,11 @@ _mm_srli_pi32(__m64 __m, int __count)
/// \param __count
///A 64-bit integer vector interpreted as a single 64-bit integer.
/// \returns A 64-bit integer vector containing the right-shifted value.
-static __inline__ __m64 __DEFAULT_FN_ATTRS
+static _
@@ -150,8 +150,8 @@ TARGET_BUILTIN(__builtin_ia32_pmovmskb, "iV8c", "ncV:64:",
"mmx,sse")
TARGET_BUILTIN(__builtin_ia32_pmulhuw, "V4sV4sV4s", "ncV:64:", "mmx,sse")
TARGET_BUILTIN(__builtin_ia32_psadbw, "V4sV8cV8c", "ncV:64:", "mmx,sse")
TARGET_BUILTIN(__builtin_ia32_pshufw, "V
@@ -614,12 +623,15 @@ _mm_shuffle_epi8(__m128i __a, __m128i __b)
///1: Clear the corresponding byte in the destination. \n
///0: Copy the selected source byte to the corresponding byte in the
///destination. \n
-///Bits [3:0] select the source byte to be copied.
@@ -811,10 +843,11 @@ _mm_slli_pi32(__m64 __m, int __count)
///A 64-bit integer vector interpreted as a single 64-bit integer.
/// \returns A 64-bit integer vector containing the left-shifted value. If
/// \a __count is greater or equal to 64, the result is set to 0.
-s
@@ -21,10 +21,29 @@ typedef int __v2si __attribute__((__vector_size__(8)));
typedef short __v4hi __attribute__((__vector_size__(8)));
typedef char __v8qi __attribute__((__vector_size__(8)));
+/* Unsigned types */
+typedef unsigned long long __v1du __attribute__ ((__vector_size
@@ -177,7 +175,10 @@ _mm_abs_epi32(__m128i __a)
/// \returns A 64-bit integer vector containing the concatenated right-shifted
///value.
#define _mm_alignr_pi8(a, b, n) \
- ((__m64)__builtin_ia32_palignr((__v8qi)(__m64)(a), (__v8qi)(__m64)(b), (n)))
+ ((__m64)__builtin_sh
@@ -124,10 +143,11 @@ _mm_cvtm64_si64(__m64 __m)
///written to the upper 32 bits of the result.
/// \returns A 64-bit integer vector of [8 x i8] containing the converted
///values.
-static __inline__ __m64 __DEFAULT_FN_ATTRS
+static __inline__ __m64 __DEFAULT_FN_ATTRS_S
@@ -0,0 +1,29 @@
+USE_XMM=
phoebewang wrote:
What these tests used for? Is your local tool uploaded unintentionally or you
want them to be reviewed as well?
https://github.com/llvm/llvm-project/pull/96540
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@@ -494,10 +520,10 @@ _mm_adds_pu16(__m64 __m1, __m64 __m2)
///A 64-bit integer vector of [8 x i8] containing the subtrahends.
/// \returns A 64-bit integer vector of [8 x i8] containing the differences of
///both parameters.
-static __inline__ __m64 __DEFAULT_FN_ATTRS
@@ -2502,10 +2509,25 @@ _mm_mulhi_pu16(__m64 __a, __m64 __b)
///A pointer to a 64-bit memory location that will receive the
conditionally
///copied integer values. The address of the memory location does not have
///to be aligned.
-static __inline__ void __DEFAULT_
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