Author: Michael Maitland Date: 2023-05-05T07:55:07-07:00 New Revision: 55e196e7718c543b4492f2949c13de003a4ba443
URL: https://github.com/llvm/llvm-project/commit/55e196e7718c543b4492f2949c13de003a4ba443 DIFF: https://github.com/llvm/llvm-project/commit/55e196e7718c543b4492f2949c13de003a4ba443.diff LOG: [RISCV] Add sifive-x280 processor with all of its extensions Add sifive-x280 processor that uses the SiFive7 scheduler model. Differential Revision: https://reviews.llvm.org/D149710 Added: Modified: clang/test/Driver/riscv-cpus.c llvm/docs/ReleaseNotes.rst llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 76325311668d8..a484b07ce330a 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -167,6 +167,20 @@ // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76" +// mcpu with default march include experimental extensions +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s +// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b" +// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d" + // Check failed cases // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index c764a50f88b22..845cee9e75455 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -175,6 +175,7 @@ Changes to the RISC-V Backend ``RISCV::parseCPU``. The ``CPUKind`` enum is no longer part of the RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and ``checkTuneCPUKind``. +* Add sifive-x280 processor. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 67b0364aa2fd7..69edacc4058c1 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -166,6 +166,22 @@ def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74", FeatureStdExtC], [TuneSiFive7]>; +def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, + [Feature64Bit, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtV, + FeatureStdExtZvl512b, + FeatureStdExtZfh, + FeatureStdExtZvfh, + FeatureStdExtZba, + FeatureStdExtZbb], + [TuneSiFive7]>; + def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, [Feature32Bit, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits