Author: Sanjay Patel Date: 2020-05-10T11:25:37-04:00 New Revision: d02b3aba37d9a18691669392ff26ec28b51741f5
URL: https://github.com/llvm/llvm-project/commit/d02b3aba37d9a18691669392ff26ec28b51741f5 DIFF: https://github.com/llvm/llvm-project/commit/d02b3aba37d9a18691669392ff26ec28b51741f5.diff LOG: [CodeGen] fix test to be (mostly) independent of LLVM optimizer; NFC This test would break with the proposed change to IR canonicalization in D79171. The test tried to do the right thing by only using -mem2reg with opt, but it was using -O3 before that step, so the opt part was meaningless. Added: Modified: clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp Removed: ################################################################################ diff --git a/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp b/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp index f0455eb31e84..77862b9f49cf 100644 --- a/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp +++ b/clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O3 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s #include <arm_mve.h> @@ -63,7 +63,7 @@ uint16x8_t test_vorrq_n_u16(uint16x8_t a) // CHECK-LABEL: @_Z16test_vcmpeqq_f1619__simd128_float16_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = fcmp oeq <8 x half> [[A:%.*]], [[B:%.*]] -// CHECK-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP0]]), !range !3 +// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP0]]) // CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16 // CHECK-NEXT: ret i16 [[TMP2]] // @@ -78,13 +78,17 @@ mve_pred16_t test_vcmpeqq_f16(float16x8_t a, float16x8_t b) // CHECK-LABEL: @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[B_COERCE:%.*]] to i32 -// CHECK-NEXT: [[TMP_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16 -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i16 [[TMP_0_EXTRACT_TRUNC]] to half -// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x half> undef, half [[TMP1]], i32 0 +// CHECK-NEXT: [[B:%.*]] = alloca half, align 2 +// CHECK-NEXT: [[TMP:%.*]] = alloca float, align 4 +// CHECK-NEXT: store float [[B_COERCE:%.*]], float* [[TMP]], align 4 +// CHECK-NEXT: [[TMP0:%.*]] = bitcast half* [[B]] to i8* +// CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[TMP]] to i8* +// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 [[TMP0]], i8* align 4 [[TMP1]], i32 2, i1 false) +// CHECK-NEXT: [[B1:%.*]] = load half, half* [[B]], align 2 +// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x half> undef, half [[B1]], i32 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x half> [[DOTSPLATINSERT]], <8 x half> undef, <8 x i32> zeroinitializer -// CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq <8 x half> [[DOTSPLAT]], [[A:%.*]] -// CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP2]]), !range !3 +// CHECK-NEXT: [[TMP2:%.*]] = fcmp oeq <8 x half> [[A:%.*]], [[DOTSPLAT]] +// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP2]]) // CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i16 // CHECK-NEXT: ret i16 [[TMP4]] // @@ -116,8 +120,8 @@ uint16x8_t test_vld1q_u16(const uint16_t *base) // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <4 x i32>* // CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32 -// CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) -// CHECK-NEXT: tail call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[VALUE:%.*]], <4 x i32>* [[TMP0]], i32 4, <4 x i1> [[TMP2]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]]) +// CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[VALUE:%.*]], <4 x i32>* [[TMP0]], i32 4, <4 x i1> [[TMP2]]) // CHECK-NEXT: ret void // void test_vst1q_p_s32(int32_t *base, int32x4_t value, mve_pred16_t p) @@ -132,7 +136,7 @@ void test_vst1q_p_s32(int32_t *base, int32x4_t value, mve_pred16_t p) // CHECK-LABEL: @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[ADDR:%.*]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = tail call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> [[TMP0]], i32 576) +// CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> [[TMP0]], i32 576) // CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 1 // CHECK-NEXT: store <2 x i64> [[TMP2]], <2 x i64>* [[ADDR]], align 8 // CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 0 @@ -146,7 +150,7 @@ int64x2_t test_vldrdq_gather_base_wb_s64(uint64x2_t *addr) // CHECK-LABEL: @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[ADDR:%.*]], align 8 -// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 64, <4 x i32> [[VALUE:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 64, <4 x i32> [[VALUE:%.*]]) // CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* [[ADDR]], align 8 // CHECK-NEXT: ret void // _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
