Author: abadouh Date: Tue Jul 5 07:24:14 2016 New Revision: 274542 URL: http://llvm.org/viewvc/llvm-project?rev=274542&view=rev Log: [X86][AVX512F] add float/double abs intrinsics add abs intrinsics that use native LLVM-IR. change _mm512_mask[z]_and_epi{32|64} to use select intrinsic
Differential Revision: http://reviews.llvm.org/D21973 Modified: cfe/trunk/lib/Headers/avx512fintrin.h cfe/trunk/test/CodeGen/avx512f-builtins.c Modified: cfe/trunk/lib/Headers/avx512fintrin.h URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx512fintrin.h?rev=274542&r1=274541&r2=274542&view=diff ============================================================================== --- cfe/trunk/lib/Headers/avx512fintrin.h (original) +++ cfe/trunk/lib/Headers/avx512fintrin.h Tue Jul 5 07:24:14 2016 @@ -515,19 +515,16 @@ _mm512_and_epi32(__m512i __a, __m512i __ static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_mask_and_epi32(__m512i __src, __mmask16 __k, __m512i __a, __m512i __b) { - return (__m512i) __builtin_ia32_pandd512_mask((__v16si) __a, - (__v16si) __b, - (__v16si) __src, - (__mmask16) __k); + return (__m512i) __builtin_ia32_selectd_512 ((__mmask16) __k, + (__v16si) _mm512_and_epi32(__a, __b), + (__v16si) __src); } + static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_maskz_and_epi32(__mmask16 __k, __m512i __a, __m512i __b) { - return (__m512i) __builtin_ia32_pandd512_mask((__v16si) __a, - (__v16si) __b, - (__v16si) - _mm512_setzero_si512 (), - (__mmask16) __k); + return (__m512i) _mm512_mask_and_epi32(_mm512_setzero_si512 (), + __k, __a, __b); } static __inline__ __m512i __DEFAULT_FN_ATTRS @@ -539,19 +536,16 @@ _mm512_and_epi64(__m512i __a, __m512i __ static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_mask_and_epi64(__m512i __src, __mmask8 __k, __m512i __a, __m512i __b) { - return (__m512i) __builtin_ia32_pandq512_mask ((__v8di) __a, - (__v8di) __b, - (__v8di) __src, - (__mmask8) __k); + return (__m512i) __builtin_ia32_selectq_512 ((__mmask8) __k, + (__v8di) _mm512_and_epi64(__a, __b), + (__v8di) __src); } + static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_maskz_and_epi64(__mmask8 __k, __m512i __a, __m512i __b) { - return (__m512i) __builtin_ia32_pandq512_mask ((__v8di) __a, - (__v8di) __b, - (__v8di) - _mm512_setzero_si512 (), - (__mmask8) __k); + return (__m512i) _mm512_mask_and_epi64((__v8di)_mm512_setzero_si512 (), + __k, __a, __b); } static __inline__ __m512i __DEFAULT_FN_ATTRS @@ -9539,6 +9533,30 @@ _mm512_set_ps (float __A, float __B, flo _mm512_set_ps((e15),(e14),(e13),(e12),(e11),(e10),(e9),(e8),(e7),(e6),(e5), \ (e4),(e3),(e2),(e1),(e0)) +static __inline__ __m512 __DEFAULT_FN_ATTRS +_mm512_abs_ps(__m512 A) +{ + return (__m512)_mm512_and_epi32(_mm512_set1_epi32(0x7FFFFFFF),(__m512i)A) ; +} + +static __inline__ __m512 __DEFAULT_FN_ATTRS +_mm512_mask_abs_ps(__m512 W, __mmask16 K, __m512 A) +{ + return (__m512)_mm512_mask_and_epi32((__m512i)W, K, _mm512_set1_epi32(0x7FFFFFFF),(__m512i)A) ; +} + +static __inline__ __m512d __DEFAULT_FN_ATTRS +_mm512_abs_pd(__m512d A) +{ + return (__m512d)_mm512_and_epi64(_mm512_set1_epi64(0x7FFFFFFFFFFFFFFF),(__v8di)A) ; +} + +static __inline__ __m512d __DEFAULT_FN_ATTRS +_mm512_mask_abs_pd(__m512d W, __mmask8 K, __m512d A) +{ + return (__m512d)_mm512_mask_and_epi64((__v8di)W, K, _mm512_set1_epi64(0x7FFFFFFFFFFFFFFF),(__v8di)A); +} + #undef __DEFAULT_FN_ATTRS #endif // __AVX512FINTRIN_H Modified: cfe/trunk/test/CodeGen/avx512f-builtins.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx512f-builtins.c?rev=274542&r1=274541&r2=274542&view=diff ============================================================================== --- cfe/trunk/test/CodeGen/avx512f-builtins.c (original) +++ cfe/trunk/test/CodeGen/avx512f-builtins.c Tue Jul 5 07:24:14 2016 @@ -1410,25 +1410,33 @@ __mmask8 test_mm512_mask_cmp_epu64_mask( __m512i test_mm512_mask_and_epi32(__m512i __src,__mmask16 __k, __m512i __a, __m512i __b) { // CHECK-LABEL: @test_mm512_mask_and_epi32 - // CHECK: @llvm.x86.avx512.mask.pand.d.512 + // CHECK: and <16 x i32> + // CHECK: %[[MASK:.*]] = bitcast i16 %{{.*}} to <16 x i1> + // CHECK: select <16 x i1> %[[MASK]], <16 x i32> %{{.*}}, <16 x i32> %{{.*}} return _mm512_mask_and_epi32(__src, __k,__a, __b); } __m512i test_mm512_maskz_and_epi32(__mmask16 __k, __m512i __a, __m512i __b) { // CHECK-LABEL: @test_mm512_maskz_and_epi32 - // CHECK: @llvm.x86.avx512.mask.pand.d.512 + // CHECK: and <16 x i32> + // CHECK: %[[MASK:.*]] = bitcast i16 %{{.*}} to <16 x i1> + // CHECK: select <16 x i1> %[[MASK]], <16 x i32> %{{.*}}, <16 x i32> %{{.*}} return _mm512_maskz_and_epi32(__k,__a, __b); } __m512i test_mm512_mask_and_epi64(__m512i __src,__mmask8 __k, __m512i __a, __m512i __b) { // CHECK-LABEL: @test_mm512_mask_and_epi64 - // CHECK: @llvm.x86.avx512.mask.pand.q.512 + // CHECK: %[[AND_RES:.*]] = and <8 x i64> + // CHECK: %[[MASK:.*]] = bitcast i8 %{{.*}} to <8 x i1> + // CHECK: select <8 x i1> %[[MASK]], <8 x i64> %[[AND_RES]], <8 x i64> %{{.*}} return _mm512_mask_and_epi64(__src, __k,__a, __b); } __m512i test_mm512_maskz_and_epi64(__mmask8 __k, __m512i __a, __m512i __b) { // CHECK-LABEL: @test_mm512_maskz_and_epi64 - // CHECK: @llvm.x86.avx512.mask.pand.q.512 + // CHECK: %[[AND_RES:.*]] = and <8 x i64> + // CHECK: %[[MASK:.*]] = bitcast i8 %{{.*}} to <8 x i1> + // CHECK: select <8 x i1> %[[MASK]], <8 x i64> %[[AND_RES]], <8 x i64> %{{.*}} return _mm512_maskz_and_epi64(__k,__a, __b); } @@ -7506,3 +7514,32 @@ __m512d test_mm512_setzero_pd() // CHECK: zeroinitializer return _mm512_setzero_pd(); } + +__m512d test_mm512_abs_pd(__m512d a){ + // CHECK-LABEL: @test_mm512_abs_pd + // CHECK: and <8 x i64> + return _mm512_abs_pd(a); +} + +__m512d test_mm512_mask_abs_pd (__m512d __W, __mmask8 __U, __m512d __A){ + // CHECK-LABEL: @test_mm512_mask_abs_pd + // CHECK: %[[AND_RES:.*]] = and <8 x i64> + // CHECK: %[[MASK:.*]] = bitcast i8 %{{.*}} to <8 x i1> + // CHECK: select <8 x i1> %[[MASK]], <8 x i64> %[[AND_RES]], <8 x i64> %{{.*}} + return _mm512_mask_abs_pd (__W,__U,__A); +} + +__m512 test_mm512_abs_ps(__m512 a){ + // CHECK-LABEL: @test_mm512_abs_ps + // CHECK: and <16 x i32> + return _mm512_abs_ps(a); +} + +__m512 test_mm512_mask_abs_ps(__m512 __W, __mmask16 __U, __m512 __A){ + // CHECK-LABEL: @test_mm512_mask_abs_ps + // CHECK: and <16 x i32> + // CHECK: %[[MASK:.*]] = bitcast i16 %{{.*}} to <16 x i1> + // CHECK: select <16 x i1> %[[MASK]], <16 x i32> %{{.*}}, <16 x i32> %{{.*}} + return _mm512_mask_abs_ps( __W, __U, __A); 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