Author: aemerson Date: Thu Jul 13 08:36:01 2017 New Revision: 307919 URL: http://llvm.org/viewvc/llvm-project?rev=307919&view=rev Log: [AArch64] Add support for handling the +sve target feature.
This also adds the appropriate predefine for SVE if enabled. Differential Revision: https://reviews.llvm.org/D35118 Modified: cfe/trunk/lib/Basic/Targets.cpp cfe/trunk/test/Preprocessor/aarch64-target-features.c Modified: cfe/trunk/lib/Basic/Targets.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=307919&r1=307918&r2=307919&view=diff ============================================================================== --- cfe/trunk/lib/Basic/Targets.cpp (original) +++ cfe/trunk/lib/Basic/Targets.cpp Thu Jul 13 08:36:01 2017 @@ -6251,7 +6251,8 @@ class AArch64TargetInfo : public TargetI enum FPUModeEnum { FPUMode, - NeonMode + NeonMode = (1 << 0), + SveMode = (1 << 1) }; unsigned FPU; @@ -6385,12 +6386,15 @@ public: Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4"); - if (FPU == NeonMode) { + if (FPU & NeonMode) { Builder.defineMacro("__ARM_NEON", "1"); // 64-bit NEON supports half, single and double precision operations. Builder.defineMacro("__ARM_NEON_FP", "0xE"); } + if (FPU & SveMode) + Builder.defineMacro("__ARM_FEATURE_SVE", "1"); + if (CRC) Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); @@ -6426,7 +6430,8 @@ public: return Feature == "aarch64" || Feature == "arm64" || Feature == "arm" || - (Feature == "neon" && FPU == NeonMode); + (Feature == "neon" && (FPU & NeonMode)) || + (Feature == "sve" && (FPU & SveMode)); } bool handleTargetFeatures(std::vector<std::string> &Features, @@ -6440,7 +6445,9 @@ public: for (const auto &Feature : Features) { if (Feature == "+neon") - FPU = NeonMode; + FPU |= NeonMode; + if (Feature == "+sve") + FPU |= SveMode; if (Feature == "+crc") CRC = 1; if (Feature == "+crypto") Modified: cfe/trunk/test/Preprocessor/aarch64-target-features.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/aarch64-target-features.c?rev=307919&r1=307918&r2=307919&view=diff ============================================================================== --- cfe/trunk/test/Preprocessor/aarch64-target-features.c (original) +++ cfe/trunk/test/Preprocessor/aarch64-target-features.c Thu Jul 13 08:36:01 2017 @@ -37,6 +37,7 @@ // CHECK-NOT: __ARM_PCS_VFP 1 // CHECK-NOT: __ARM_SIZEOF_MINIMAL_ENUM 1 // CHECK-NOT: __ARM_SIZEOF_WCHAR_T 2 +// CHECK-NOT: __ARM_FEATURE_SVE // RUN: %clang -target aarch64_be-eabi -x c -E -dM %s -o - | FileCheck %s -check-prefix CHECK-BIGENDIAN // CHECK-BIGENDIAN: __ARM_BIG_ENDIAN 1 @@ -84,6 +85,10 @@ // CHECK-GENERIC: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" // RUN: %clang -target aarch64 -mtune=cyclone -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MTUNE-CYCLONE %s + +// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+sve -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SVE %s +// CHECK-SVE: __ARM_FEATURE_SVE 1 + // ================== Check whether -mtune accepts mixed-case features. // RUN: %clang -target aarch64 -mtune=CYCLONE -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MTUNE-CYCLONE %s // CHECK-MTUNE-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+zcm" "-target-feature" "+zcz" _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits