On Mon, Nov 09, 2009 at 07:44:20PM -0500, Kevin O'Connor wrote:
That is, instead of defining a compile time parameter, I wonder if the
default should be to msleep and only use the cmos method when qemu is
detected - the cmos thing is really qemu specific anyway. Gleb - do
you know a good way
On 11/10/2009 01:44 AM, Kevin O'Connor wrote:
On Thu, Nov 05, 2009 at 03:00:45PM +0100, Magnus Christensson wrote:
Ok. Changed patches attached.
Thanks Magnus. I've committed patches 1-3 and 6. I have a question
on patch 4:
@@ -91,6 +93,12 @@ smp_probe(void)
u32 val =
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson myle...@gmail.com wrote:
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng zheng@amd.com wrote:
By we, please tell me if it has anything to do with the chipset and
mainboard code.
Sorry I wasn't clear. I meant maybe coreboot needs a generic chip
Magnus Christensson wrote:
I'm not sure how work is divided between Coreboot and Seabios. Does
Coreboot do all the machine specific initialization?
This is the idea.
Then the LINT LVTs should already have been initialized.
How are you using coreboot+SeaBIOS? Are you using the QEMU coreboot
On Tue, Nov 10, 2009 at 9:45 AM, Myles Watson myle...@gmail.com wrote:
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson myle...@gmail.com wrote:
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng zheng@amd.com wrote:
By we, please tell me if it has anything to do with the chipset and
mainboard
Myles Watson wrote:
On Tue, Nov 10, 2009 at 9:45 AM, Myles Watson myle...@gmail.com
mailto:myle...@gmail.com wrote:
On Mon, Nov 9, 2009 at 10:06 PM, Myles Watson myle...@gmail.com
mailto:myle...@gmail.com wrote:
On Mon, Nov 9, 2009 at 9:54 PM, Bao, Zheng
Could you send me your devicetree.cb or Config.lb?
My thought is that you can put chip drivers/generic/generic around the
video card so that it doesn't get the 780 ops.
Does it get any 780 ops at all? I'd think it only does when a struct
pci_driver is catching it?
I haven't seen
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au wrote:
Another observation I made was that by setting the debug_level to BIOS_CRIT,
instead of dying at the usual spot in disable_car() and stopping, coreboot
would reset continuously (cycling every 1-2
Author: stepan
Date: 2009-11-10 22:17:15 + (Tue, 10 Nov 2009)
New Revision: 4932
Modified:
trunk/src/arch/i386/boot/acpi.c
trunk/src/arch/i386/boot/wakeup.S
trunk/src/arch/i386/include/arch/acpi.h
trunk/src/arch/i386/lib/c_start.S
Log:
* Simplify acpi_add_table
* fix some
Rudolf Marek wrote:
Hi
Sorry I tried to get it working on K8 but got distracted by the
network support
for SerialICE and network console for coreboot ;)
How's that going?
I think I can Acked-by: Rudolf Marek r.ma...@assembler.cz
Thanks, r4932
Although I would
prefer to have the wakeup
On Tue, Nov 10, 2009 at 1:26 PM, Nathan Williams nat...@traverse.com.au wrote:
Marc Jones wrote:
On Fri, Nov 6, 2009 at 7:57 AM, Nathan Williams nat...@traverse.com.au
wrote:
Another observation I made was that by setting the debug_level to
BIOS_CRIT,
instead of dying at the usual spot in
Hello,
Not really related to coreboot but I thought this was pretty cool and
wanted to share.
http://www.mp3car.com/blogs/137150_SEMA-2009--Mavizen-0-Carbon-Linux-Electric-Motorcycle.html
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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coreboot mailing list:
Config.lb and lspci of mahogany and mahogany_fam10 are attached.
Zheng
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org] On Behalf Of Myles Watson
Sent: Tuesday, November 10, 2009 11:46 PM
To: Bao, Zheng
Cc: Stefan Reinauer; Marc
Config.lb_mahogany_k8
chip southbridge/amd/rs780
device pci 0.0 on end # HT 0x9600
device pci 1.0 on # Internal Graphics P2P bridge 0x9602
chip drivers/pci/onboard
device pci 5.0 on end # Internal Graphics 0x9615
Hi, All,
Have the repository added the authorization? What happened?
Zheng
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http://www.coreboot.org/mailman/listinfo/coreboot
The onboard was not removed because all my work have based on 4924,
which has remove the onboard. If I need try the new code, I will remove
it.
Zheng
-Original Message-
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org] On Behalf Of Peter Stuge
Sent: Wednesday,
This happens on svn port. https seems to work well.
Zheng
-Original Message-
From: coreboot-bounces+zheng.bao=amd@coreboot.org
[mailto:coreboot-bounces+zheng.bao=amd@coreboot.org] On Behalf Of
Bao, Zheng
Sent: Wednesday, November 11, 2009 11:38 AM
To: coreboot@coreboot.org
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