Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5369 to
the coreboot repository. This caused the following
changes:
Change Log:
it's a long term, give the compiler a chance to breathe .. ;-)
Signed-off-by: Stefan Reinauer
Acked
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5368 to
the coreboot repository. This caused the following
changes:
Change Log:
clean up age old via epia target.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Buil
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5367 to
the coreboot repository. This caused the following
changes:
Change Log:
drop the use of function pointers from romcc code.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan
Author: stepan
Date: Wed Apr 7 05:41:39 2010
New Revision: 5369
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5369
Log:
it's a long term, give the compiler a chance to breathe .. ;-)
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/northbridge/via/vt
Author: stepan
Date: Wed Apr 7 05:40:37 2010
New Revision: 5368
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5368
Log:
clean up age old via epia target.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/Kconfig
trunk/src/cpu/x86/mtrr/earlymtrr.c
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5366 to
the coreboot repository. This caused the following
changes:
Change Log:
fix epia-m700 compilation, and remove more warnings.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan
Author: stepan
Date: Wed Apr 7 05:11:28 2010
New Revision: 5367
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5367
Log:
drop the use of function pointers from romcc code.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/mainboard/digitallogic/msm586s
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5365 to
the coreboot repository. This caused the following
changes:
Change Log:
no duplicate names in cmos.layout.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Buil
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5364 to
the coreboot repository. This caused the following
changes:
Change Log:
switch some ROMCC boards back to ROMCC.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
On 4/7/10 1:05 AM, secretoc...@gmx.de wrote:
> Hi,
>
> I've got an HP nx6310 notebook with Linux as operating system and I'm
> thinking of trying coreboot to get rid of the non-free HP BIOS.
> Though I'm quite confident that the chipset is supported, it'll be nice if
> someone would confirm that
Author: stepan
Date: Wed Apr 7 04:30:57 2010
New Revision: 5366
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5366
Log:
fix epia-m700 compilation, and remove more warnings.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/mainboard/artecgroup/dbe61/ma
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5363 to
the coreboot repository. This caused the following
changes:
Change Log:
"no warnings day"
last round for today. still warnings - help appreciated.
Signed-off-by: Stefan Rein
Author: stepan
Date: Wed Apr 7 04:09:54 2010
New Revision: 5365
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5365
Log:
no duplicate names in cmos.layout.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/mainboard/asrock/939a785gmh/cmos.layout
Modifi
Author: stepan
Date: Wed Apr 7 04:06:53 2010
New Revision: 5364
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5364
Log:
switch some ROMCC boards back to ROMCC.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/drivers/generic/debug/debug_dev.c
trun
On Tue, Apr 06, 2010 at 04:21:57PM -0600, Myles Watson wrote:
> I'm seeing code reads to memset() in coreboot_ram interleaved with byte
> writes to somewhere high on the stack (_estack -0x1fC). This is a k8.
>
> I can't find the place during the RAM stage when we are calling memset with
> caches
Author: stepan
Date: Wed Apr 7 03:44:04 2010
New Revision: 5363
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5363
Log:
"no warnings day"
last round for today. still warnings - help appreciated.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/mainboa
Author: stepan
Date: Wed Apr 7 03:41:01 2010
New Revision: 5362
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5362
Log:
oops... this is a critical issue. Some boards in the tree don't compile with
romcc even though they don't have CAR either. We need to check all boards and
fix those
Author: stepan
Date: Wed Apr 7 02:38:09 2010
New Revision: 5361
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5361
Log:
- unify use of SB_HT_CHAIN_UNITID_OFFSET_ONLY
- cleanup reset
- some minor warning fixes.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
t
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5360 to
the coreboot repository. This caused the following
changes:
Change Log:
fix CK804 boards.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Build Log:
Compilati
Author: stepan
Date: Wed Apr 7 01:55:17 2010
New Revision: 5360
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5360
Log:
fix CK804 boards.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c
trunk/src/south
Hi,
I've got an HP nx6310 notebook with Linux as operating system and I'm thinking
of trying coreboot to get rid of the non-free HP BIOS.
Though I'm quite confident that the chipset is supported, it'll be nice if
someone would confirm that and perhaps give further instructions on how to use
cor
> >> Now that we have Kconfig, I think this check can disappear. Is there a
> way
> >> to un-define CONFIG_RAMTOP?
> > With RAMTOP being
> >
> > config RAMTOP
> > hex
> > default 0x20
> >
> > it can't happen.
> >
> > But I didn't want to change the rough logical flow with self-acked code,
> >
> Maybe you can run under SimNow and use a memory access breakpoint?
Good idea. How do you tell in SimNow if an access is cached or not?
Thanks,
Myles
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coreboot mailing list: coreboot@coreboot.org
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-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Myles Watson wrote:
>> Maybe you can run under SimNow and use a memory access breakpoint?
> Good idea. How do you tell in SimNow if an access is cached or not?
Dont know maybe you can check CPU state after a breakpoint?
Rudolf
>
> Thanks,
> Myles
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer "stepan" checked in revision 5359 to
the coreboot repository. This caused the following
changes:
Change Log:
No warnings day, next round.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Build Log
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Maybe you can run under SimNow and use a memory access breakpoint?
Rudolf
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Version: GnuPG v1.4.10 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iEYEARECAAYFAku7tQsACgkQ3J9wPJqZRNVLPQCeOgzlrj7S
wasn't meant to be private only.
On 4/7/10 12:24 AM, Stefan Reinauer wrote:
> On 4/7/10 12:06 AM, Myles Watson wrote:
>
>>
>>
>>> -Original Message-
>>> From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
>>> On Behalf Of repository service
>>> Sent: Tuesd
I'm seeing code reads to memset() in coreboot_ram interleaved with byte
writes to somewhere high on the stack (_estack -0x1fC). This is a k8.
I can't find the place during the RAM stage when we are calling memset with
caches disabled. Does this ring a bell for anyone?
Thanks,
Myles
--
corebo
> -Original Message-
> From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org]
> On Behalf Of repository service
> Sent: Tuesday, April 06, 2010 3:50 PM
> To: coreboot@coreboot.org
> Subject: [coreboot] [commit] r5359 - in trunk/src: .
> cpu/amd/model_10xxxcpu/amd/model
Author: stepan
Date: Tue Apr 6 21:50:21 2010
New Revision: 5359
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5359
Log:
No warnings day, next round.
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/src/Kconfig
trunk/src/cpu/amd/model_10xxx/init_cpus.c
Author: stepan
Date: Tue Apr 6 21:49:31 2010
New Revision: 5358
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5358
Log:
fam10 acpi fix
Signed-off-by: Stefan Reinauer
Acked-by: Marc Jones
Modified:
trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c
Modified: trunk/src/northbri
If you have never done a bios before I would take a more limited scope
project, maybe getting v4 working on geode, which we really need.
I would think twice about the marvell, that may be too much for the summer.
ron
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailma
On 04/06/2010 02:56 PM, austi...@msu.edu wrote:
Hi. My name's Rob Austin, I'm a computer engineering major at Michigan
State University. I got on IRC for a bit a week or so ago and chatted
with a few people about some of the proposed ideas. I've had some time
to think and read more about what I
Hi. My name's Rob Austin, I'm a computer engineering major at
Michigan State University. I got on IRC for a bit a week or so ago
and chatted with a few people about some of the proposed ideas. I've
had some time to think and read more about what I could do for
coreboot, and I'd like to g
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