Stefan Reinauer ste...@coresystems.de writes:
Nice... !
I've been wondering before... why this odd approach with read8x and
gs:... instead of just doing normal read8/16/32 ?
Primarily to enable mapping in 64-bit space, I suppose. I guess we
could map AMD fam10 mmio config space into 32
Ed Swierk eswi...@aristanetworks.com writes:
Anoyone familiar with the mcp55 who can shed some light on what this
write is supposed to accomplish and perhaps also on why it succeeds
using the IO config mechanism when mmconf fails?
That write has always caused a hang on Arista boards, even
Marc Jones marcj...@gmail.com writes:
That code is doing something a little ugly to make the two cs
registers use the one mask register. It was ported from a routine that
assumed that GET_NB32() fixed the alignment. Maybe add a comment about
why that is happening.
I assumed as much. I'll see
On Tue, Apr 13, 2010 at 12:35 AM, Arne Georg Gleditsch
arne.gledit...@numascale.com wrote:
I'd like to push this mmconf patch upstream in some shape or form, so if
anyone would like to chime in how to approach this I'd be glad. I could
just wrap the offending line with #if
Author: stepan
Date: Tue Apr 13 12:01:14 2010
New Revision: 5417
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5417
Log:
Speed up coreboot_ram loading by moving the decompression stack
into the cached area. Back to 469ms until coreboot_ram is actually
running on epia-cn
Author: stepan
Date: Tue Apr 13 12:04:35 2010
New Revision: 5418
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5418
Log:
use the standard udelay on sc520.
Acked-by: Stefan Reinauer ste...@coresystems.de
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 5418 to
the coreboot repository. This caused the following
changes:
Change Log:
use the standard udelay on sc520.
Acked-by: Stefan Reinauer ste...@coresystems.de
Signed-off-by:
On 13.04.2010 09:28, Arne Georg Gleditsch wrote:
Stefan Reinauer ste...@coresystems.de writes:
Nice... !
I've been wondering before... why this odd approach with read8x and
gs:... instead of just doing normal read8/16/32 ?
Primarily to enable mapping in 64-bit space, I suppose. I
Hi Ed,
hi Yinghai,
On 13.04.2010 10:32, Ed Swierk wrote:
The logic in mcp55_early_setup_car.c seems at least partially based on
ck804_early_setup_car.c. Maybe the write to 0x78 is just a leftover
copy-and-paste scrap?
Didn't you have access to the MCP55 docs? Not sure if you still have
Author: stepan
Date: Tue Apr 13 15:43:35 2010
New Revision: 5419
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5419
Log:
clean up LD scripts and add some comments and proper license headers
where applicable.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan
Author: stepan
Date: Tue Apr 13 15:48:20 2010
New Revision: 5420
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5420
Log:
fix timer choice in Kconfig. HAVE_INIT_TIMER is selected correctly, no need to
mention it explicitly.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 5419 to
the coreboot repository. This caused the following
changes:
Change Log:
clean up LD scripts and add some comments and proper license headers
where applicable.
Signed-off-by:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer stepan checked in revision 5420 to
the coreboot repository. This caused the following
changes:
Change Log:
fix timer choice in Kconfig. HAVE_INIT_TIMER is selected correctly, no need to
mention it explicitly.
On 04/12/2010 05:58 PM, Andriy Gapon wrote:
on 09/04/2010 19:52 Vadim Girlin said the following:
Here is code fragment I mentioned - some bit is set then reset:
(Not sure now that this code runs at all)
Vadim,
cool work!
BTW:
http://www.rom.by/forum/Gigabyte_DualBIOS
:-)
I've seen
Hi Xavi,
Thanks for your interest in coreboot. This is a long email! :)
I have made some small comments below.
On Mon, Apr 12, 2010 at 3:07 PM, xdrudis xdru...@tinet.cat wrote:
Hello.
First things first: thank you all for working in coreboot, yet another
free software project I wouldn't
Hi All
Intel® 845G chipset
Southbridge 82801
P4 2.4GHz
From Compaq Evo D310 DT (Custom Mobo, P4B266-VMX)
Any recomemendations?
Which payload to choose? I want to start with a basic one, will be using
Linux mostly, but I do want to try XP and DOS perhaps.
SeaBios seems good, but on the Wiki, it
On 04/09/2010 08:05 PM, Rudolf Marek wrote:
Also there is some moment in bios code about test reg 2F @ LDN F4 - it
is toggled in some place and this could be important - may be enabling
some undocumented features.
The test register is only RW when written from LDN F4.
Thanks,
Rudolf
hi,
the only AMD 780 mainboard which coreboot support is mahogany. But there
will be pretty much more, since i am trying to do several 780 mainboard
porting.i think it's pretty find that we can port coreboot to this
mainboard. I would like to add this mainboard into my GSOC mainboard list.
On 04/12/2010 05:58 PM, Andriy Gapon wrote:
on 09/04/2010 19:52 Vadim Girlin said the following:
Here is code fragment I mentioned - some bit is set then reset:
(Not sure now that this code runs at all)
Vadim,
cool work!
BTW:
http://www.rom.by/forum/Gigabyte_DualBIOS
:-)
I've seen
On 13.04.2010 19:18, Vadim Girlin wrote:
On 04/09/2010 08:05 PM, Rudolf Marek wrote:
Also there is some moment in bios code about test reg 2F @ LDN F4 - it
is toggled in some place and this could be important - may be enabling
some undocumented features.
The test register is only
Author: stepan
Date: Tue Apr 13 22:34:58 2010
New Revision: 125
URL: http://tracker.coreboot.org/trac/filo/changeset/125
Log:
add extern declaration of UNIQUE_BUF (fixes CONFIG_EXPERIMENTAL compilation)
Signed-off-by: Cai Bai Yin caibaiyin@gmail.com
Acked-by: Stefan Reinauer
On 4/12/10 10:56 AM, baiyin cai wrote:
Hi,
attached patch does:
- add extern declaration of UNIQUE_BUF
Signed-off-by: Cai Bai Yin caibaiyin@gmail.com
mailto:caibaiyin@gmail.com
Thanks... committed as r125
--
coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br.
Tel.:
So you advice me to install coreboot on it?
the motherboard is not mentioned on the website, but the chipset is!
Thanks.
On Tue, Apr 13, 2010 at 6:44 PM, Qing Pei Wang wangqing...@gmail.comwrote:
if you want to try xp/DOS, Seabios would be the only choice. and it is
unnecessary to use kernel
Author: stepan
Date: Tue Apr 13 23:29:43 2010
New Revision: 5421
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5421
Log:
fix a trivial warning when yabel with direct hw access is enabled.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer
Author: stepan
Date: Tue Apr 13 23:31:42 2010
New Revision: 5422
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5422
Log:
ip1000: fix seabios start, fix flash gpio detection
simplify i82830 code.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer
On Tue, Apr 13, 2010 at 09:44:02AM -0600, Marc Jones wrote:
Hi Xavi,
Thanks for your interest in coreboot. This is a long email! :)
I'm bad at summarizing. Sorry.
VGA BIOS is not required. You could have a headless system. Or a
system with a framebuffer driver like Geode.
Headless
OK, but I sent some disassembled logs - the bios is proprietary, isn't?
Anyway all I want is to say that i don't want to violate any rules.
Any info that I sent was supposed to help the developers.
If some of my posts violates some rules - I'm sorry.
So probably you should say on coreboot page
hi,
On Wed, Apr 14, 2010 at 5:51 AM, xdrudis xdru...@tinet.cat wrote:
On Tue, Apr 13, 2010 at 09:44:02AM -0600, Marc Jones wrote:
Hi Xavi,
Thanks for your interest in coreboot. This is a long email! :)
I'm bad at summarizing. Sorry.
VGA BIOS is not required. You could have a
Hello,
I've been trying to bring coreboot up on an EP80579 reference platform
(not Truxton) and I have thus far been thwarted.
I'm using svn revision 5442 and the boot hangs with just the welcome to
coreboot line:
coreboot-4.0-r5422M Tue Apr 13 18:13:08 PDT 2010 starting...
I've put
On Tue, Apr 13, 2010 at 12:35 AM, Arne Georg Gleditsch
arne.gledit...@numascale.com wrote:
That's a valuable data point. I'm also running with it disabled, no
apparent problems here either.
I'd like to push this mmconf patch upstream in some shape or form, so if
anyone would like to chime in
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