Re: [coreboot] H8QME 128GB RAM not Booting

Myles Watson escribió: I have a board here with 128GB Ram (16*8GB) and it won't boot. It hangs at Copying data from cache to RAM -- switching to use RAM as stack So at least ram initialization is done, but why does it stop booting? Some values I have to increment in order to use more RAM?

[coreboot] [commit] r5544 - in trunk/src/mainboard/wyse: . s50

Author: stepan Date: Fri May 14 11:45:29 2010 New Revision: 5544 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5544 Log: This patch cleanes up the Wyse S50 port and unifies the memmory regions with Geode LX , adds gpl2 headers plus some white space fixes. This is build and boot

[coreboot] [commit] r5545 - in trunk/src: cpu/amd/model_gx1 cpu/intel/slot_1 cpu/intel/slot_2 cpu/intel/socket_PGA370 mainboard/a-trend mainboard/a-trend/atc-6220 mainboard/a-trend/atc-6240 mainboard/

Author: stepan Date: Fri May 14 11:48:05 2010 New Revision: 5545 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5545 Log: license header fixes Signed-off-by: Nils Jacobs njaco...@hetnet.nl Acked-by: Stefan Reinauer ste...@coresystems.de Modified:

[coreboot] [commit] r5546 - trunk/src/northbridge/amd/gx2

Author: stepan Date: Fri May 14 11:56:46 2010 New Revision: 5546 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5546 Log: Fix warning. Hardware tested and didn't change behavior. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de

[coreboot] [commit] r5547 - trunk/src/northbridge/amd/gx2

Author: stepan Date: Fri May 14 11:59:59 2010 New Revision: 5547 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5547 Log: fix SeaBIOS loading on GX2. Signed-off-by: Nils Jacobs njaco...@hetnet.nl Acked-by: Stefan Reinauer ste...@coresystems.de Modified:

[coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

This patch should fix the hda interrupt lost problem on the Wyse S50 Move CS5535 specific setup from GX2 driver to CS5535. To apply this patch you need to cp src/northbridge/amd/gx2/chipsetinit.c src/southbridge/amd/cs5535/ Signed-off-by: Stefan Reinauer ste...@coresystems.de Index:

[coreboot] #163: Board still requires RAMBASE 1MB

#163: Board still requires RAMBASE 1MB -+-- Reporter: oxygene | Owner: ste...@… Type: defect|Status: new Priority: minor | Milestone:

[coreboot] How is the Status for 845 Chipset (Akimbo 1150 / Thomson IP1101) ?

Hi, i know that someone is trying to get coreboot to run on the Akimbo 1150 STB with Intel 845 Chipset. I have a Thomson IP1101 which has the same board in it and i'd like to know if there is any news about runnin coreboot on this platform. Thanks! Carsten -- coreboot mailing list:

Re: [coreboot] How is the Status for 854 Chipset (Akimbo 1150 / Thomson IP1101) ?

On Fri, 14 May 2010 11:02:54 + (GMT), Carsten Müller muellinger...@yahoo.de wrote: Hi, i know that someone is trying to get coreboot to run on the Akimbo 1150 STB with Intel 845 Chipset. I have a Thomson IP1101 which has the same board in it and i'd like to know if there is any news

Re: [coreboot] How is the Status for 854 Chipset (Akimbo 1150 / Thomson IP1101) ?

Hi Joseph, thanks four your reply. It is really interesting and i'll stay tuned! :-) I have some problems getting linux the mambux way that blocks my plan making a linux based NAS with the IP1101. Until theres anything new from your site i'll keep using it wathing some IPTV :-) You rock!

Re: [coreboot] [PATCH] watchdog mcp55's codec initialization loops

On Fri, May 14, 2010 at 07:17:11AM -0400, Stefan Reinauer wrote: Could you please send a log file containing the output of the new azalia driver? PCI: 00:06.1 init Azalia: codec type: Azalia Azalia: base = fc14 Azalia: codec_mask = 01 Azalia: Initializing codec #0 PCI:

Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

2010/5/14 Keith Hui buu...@gmail.com The original patch was unclean as pork (didn't apply cleanly). Please use this one instead. Thanks Joseph. And edit your board's romstage similar to patch below: Index: src/mainboard/asus/p2b-ls/romstage.c

Re: [coreboot] [PATCH] watchdog mcp55's codec initialization loops

On 5/14/10 4:29 PM, Joe Korty wrote: PS: I'm curious, why does coreboot need to initialize the audio? It has no need of audio itself, and AFAIK, no payload which follows coreboot needs audio either. The wiring of the codec is mainboard specific and all Windows and Linux drivers expect the

Re: [coreboot] it boots! [was: re: H8DME-2 woes, continued....]

On Thu, May 13, 2010 at 01:17:23PM -0400, Peter Stuge wrote: Can you check which codec you have please? Linux reports this. From my laptop: [3.509587] ALSA device list: [3.509593] #0: Intel 82801DB-ICH4 with AD1981B at irq 17 Joe Korty wrote: I don't have an 'ALSA' labeled line

[coreboot] Re [PATCH] SECC Pentium 2/3 users are g onna love this

Just fund a Celeron coppermine (686), The chipset of the mainboard seams to be mostly supported so shouldn't take to long to port and test. L2 is 128kb. Mvh Anders - Reply message - Fra: Keith Hui buu...@gmail.com Dato: fre., maj 14, 2010 05:30 Emne: [coreboot] [PATCH] SECC Pentium 2/3

[coreboot] [commit] r5549 - trunk/util/superiotool

Author: uwe Date: Fri May 14 18:40:55 2010 New Revision: 5549 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5549 Log: Various superiotool fixes. - IT8671F/IT8687R: - Fix typo: Parallel port register 0x60 value is 0x03 (not 0x01). - Fix typo: APC register 0xf6 is 0x00.

[coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi

Author: stepan Date: Fri May 14 18:44:45 2010 New Revision: 5550 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5550 Log: Fix i945 ACPI for ASL Optimizing Compiler version 20100428. The values are overwritten on the fly but without the patch iasl will refuse to compile the code.

[coreboot] [PATCH] fix hd8me early-boot 50 sec stallout

Fix the SuperMicro H8DME-2 early-boot 50 sec stall. Somewhere between r5491 and r5496, a change occured which added some 30-50 seconds to the boot time of a Supermicro H8DME-2. This rises by an additional 30-50 seconds if the boot sequence decides it needs to reset-restart. The problem was

Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

2010/5/14 Keith Hui buu...@gmail.com BTW enable CAR and try again. Like this (note that it doesn't boot my asus p2b, rev 1.04): svn diff src/mainboard/asus/p2b/Kconfig Index: src/mainboard/asus/p2b/Kconfig === ---

[coreboot] [commit] r5551 - in trunk/src/northbridge/amd: amdfam10 amdk8

Author: stepan Date: Fri May 14 19:15:57 2010 New Revision: 5551 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5551 Log: more acpica fixes... The tricky part is the stuff in the AMD mainboard directories. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer

[coreboot] License changes

On Fri, May 14, 2010 at 11:48:07AM +0200, repository service wrote: Author: stepan Date: Fri May 14 11:48:05 2010 New Revision: 5545 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5545 Log: license header fixes Please don't do this kind of change to any code other than trivial

[coreboot] [PATCH] update reference tool chain

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Update

Re: [coreboot] License changes

On 5/14/10 7:17 PM, Uwe Hermann wrote: On Fri, May 14, 2010 at 11:48:07AM +0200, repository service wrote: Author: stepan Date: Fri May 14 11:48:05 2010 New Revision: 5545 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5545 Log: license header fixes Please don't do

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

Op vrijdag 14 mei 2010 13:13:39 schreef u: This patch should fix the hda interrupt lost problem on the Wyse S50 Hi Stefan, Thanks for making this patch. :) Unfortunately i have no time today to test it, maybe tomorrow evening. I quickly browsed the code, am i correct that you disabled the

Re: [coreboot] License changes

On Fri, May 14, 2010 at 07:25:51PM +0200, Stefan Reinauer wrote: Oh, it said that the license choice was at my option. Sorry for that. Maybe the header should clarify whose option is meant, then. I think we should make clear which license we assign to the code. Having Sure, we already do

Re: [coreboot] [commit] r5544 - in trunk/src/mainboard/wyse: . s50

Hi Stefan, You wrote: Author: stepan Date: Fri May 14 11:45:29 2010 New Revision: 5544 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5544 Thanks for committing! Regards,Nils. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi

repository service wrote: Fix i945 ACPI for ASL Optimizing Compiler version 20100428. The whitespace changes in this commit made it difficult to see what was actually changed. :\ //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

Op vrijdag 14 mei 2010 20:03:25 schreef u: On Fri, 14 May 2010 19:57:22 +0200, Nils njaco...@hetnet.nl wrote: Op vrijdag 14 mei 2010 13:13:39 schreef u: This patch should fix the hda interrupt lost problem on the Wyse S50 Hi Stefan, Thanks for making this patch. :) Unfortunately i

Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

Limit your DCACHE_RAM_SIZE to 0x1000 (4k). The L2 init is done post-raminit so it's not available for CAR. Your CPU only has 16k of L1 cache available for CAR. HTH Keith On Fri, May 14, 2010 at 12:51 PM, Idwer Vollering vid...@gmail.com wrote: 2010/5/14 Keith Hui buu...@gmail.com BTW enable

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

On 5/14/10 7:57 PM, Nils wrote: Op vrijdag 14 mei 2010 13:13:39 schreef u: This patch should fix the hda interrupt lost problem on the Wyse S50 Hi Stefan, Thanks for making this patch. :) Unfortunately i have no time today to test it, maybe tomorrow evening. I quickly browsed the

Re: [coreboot] [PATCH] cleanup CS5535/CS5536 specific init in GX2 code

On Fri, 14 May 2010 20:17:08 +0200, Nils njaco...@hetnet.nl wrote: Op vrijdag 14 mei 2010 20:03:25 schreef u: On Fri, 14 May 2010 19:57:22 +0200, Nils njaco...@hetnet.nl wrote: Op vrijdag 14 mei 2010 13:13:39 schreef u: This patch should fix the hda interrupt lost problem on the Wyse S50

Re: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi

On 5/14/10 8:09 PM, Peter Stuge wrote: repository service wrote: Fix i945 ACPI for ASL Optimizing Compiler version 20100428. The whitespace changes in this commit made it difficult to see what was actually changed. :\ Check out the link that comes with the mails:

Re: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi

Check out the link that comes with the mails: https://tracker.coreboot.org/trac/coreboot/changeset/5550 I do like seeing it side by side. Would it be an easy fix to change the emailed links to http instead of https? Manually editing the link to http already works. Thanks, Myles -- coreboot

Re: [coreboot] [commit] r5550 - trunk/src/northbridge/intel/i945/acpi

Stefan Reinauer wrote: The whitespace changes in this commit made it difficult to see what was actually changed. :\ Check out the link that comes with the mails: https://tracker.coreboot.org/trac/coreboot/changeset/5550 It makes it really easy to understand the patch. I agree - very

[coreboot] [commit] r5552 - in trunk/src: mainboard/intel/d945gclf mainboard/kontron/986lcd-m mainboard/roda/rk886ex northbridge/intel/i945

Author: stepan Date: Fri May 14 21:09:20 2010 New Revision: 5552 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5552 Log: i945: * fix some potential compiler issues with newer gccs * add some more comments * make 32bit accesses for feature test functions * make some objects drivers

[coreboot] [commit] r5553 - in trunk/src: arch/i386/include/arch include/cpu/x86 southbridge/intel/i82801gx

Author: stepan Date: Fri May 14 21:11:44 2010 New Revision: 5553 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5553 Log: clean up some prototypes Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified:

[coreboot] [PATCH] Move the 'USE CMOS' Kconfig question.

Move the 'USE CMOS' Kconfig question. Move the 'USE CMOS' question from the top level to the General Setup section of Kconfig. Signed-off-by: Joe Korty joe.ko...@ccur.com Index: trunk/src/Kconfig === --- trunk.orig/src/Kconfig

[coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

Promote heap sizing to first-class Kconfig citizenship. Changing the heap size is something that those, like me, with large PCI device trees need to do. Therefore heap size should appear as a normal, user-answerable question within the Kconfig build system. Also change the malloc debug message

Re: [coreboot] [PATCH] fix hd8me early-boot 50 sec stallout

On Fri, May 14, 2010 at 10:45 AM, Joe Korty joe.ko...@ccur.com wrote: Fix the SuperMicro H8DME-2 early-boot 50 sec stall. Somewhere between r5491 and r5496, a change occured which added some 30-50 seconds to the boot time of a Supermicro H8DME-2.  This rises by an additional 30-50 seconds if

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On Fri, May 14, 2010 at 1:11 PM, Joe Korty joe.ko...@ccur.com wrote: Promote heap sizing to first-class Kconfig citizenship. Changing the heap size is something that those, like me, with large PCI device trees need to do.  Therefore heap size should appear as a normal, user-answerable

[coreboot] [PATCH] Support for TI xx12 cardbus bridge

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add TI

[coreboot] [PATCH] support for two SMSC superios

See patch. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add two

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On 5/14/10 9:19 PM, Myles Watson wrote: On Fri, May 14, 2010 at 1:11 PM, Joe Korty joe.ko...@ccur.com wrote: Promote heap sizing to first-class Kconfig citizenship. Changing the heap size is something that those, like me, with large PCI device trees need to do. Therefore heap size

[coreboot] [ANNOUNCE] Getac P470 notebook support

Hi, coreboot® is running on a multitude of different computers, ranging from tiny embedded systems as small as the palm of your hand over desktop and server systems to super computers with thousands of nodes. And now this is the second i945 based notebook that can run coreboot. Thus, I am

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On Fri, May 14, 2010 at 03:19:45PM -0400, Myles Watson wrote: On Fri, May 14, 2010 at 1:11 PM, Joe Korty joe.ko...@ccur.com wrote: Promote heap sizing to first-class Kconfig citizenship. Changing the heap size is something that those, like me, with large PCI device trees need to do.

[coreboot] [commit] r5554 - in trunk/src/mainboard/gigabyte: . ga-6bxe

Author: uwe Date: Fri May 14 21:50:11 2010 New Revision: 5554 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5554 Log: Add initial support for the GIGABYTE GA-6BXE. Signed-off-by: Anders Jenbo and...@jenbo.dk Acked-by: Uwe Hermann u...@hermann-uwe.de Added:

Re: [coreboot] [CoreBoot] PATCH: Support for Gigabyte GA-6BXE

On Sun, May 09, 2010 at 03:47:05PM +0200, Patrick Georgi wrote: Am 09.05.2010 02:40, schrieb Anders Jenbo: Quick update to add my name to the headers How much of Uwe's code (which you seemed to have based the board on) is left? No issue here, the 440BX boards are dead simple, almost trivial.

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On Fri, May 14, 2010 at 1:49 PM, Joe Korty joe.ko...@ccur.com wrote: On Fri, May 14, 2010 at 03:19:45PM -0400, Myles Watson wrote: On Fri, May 14, 2010 at 1:11 PM, Joe Korty joe.ko...@ccur.com wrote: Promote heap sizing to first-class Kconfig citizenship. Changing the heap size is

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On Fri, May 14, 2010 at 03:56:00PM -0400, Myles Watson wrote: It seems like you have a pretty specific special case. :) From my point of view, large systems are the standard case and normal desktops are the oddballs. Regards, Joe Sounds like fun. It's been educational and

Re: [coreboot] PATCH: superiotool dump it8671f

On Sun, May 09, 2010 at 01:51:27AM +0200, Anders Jenbo wrote: Done, thanks for the link. I also added a link to your example dump, could be useful at some point. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org --

Re: [coreboot] [PATCH] Support for TI xx12 cardbus bridge

It looks like the generic cardbus ops would have worked for you (a little less debugging output, though). Are you planning on adding more later, or should we consider just using the default? Acked-by: Myles Watson myle...@gmail.com Thanks, Myles -- coreboot mailing list:

Re: [coreboot] [PATCH] Support for TI xx12 cardbus bridge

On Fri, May 14, 2010 at 09:23:54PM +0200, Stefan Reinauer wrote: Index: southbridge/ti/pcixx12/pcixx12.c === --- southbridge/ti/pcixx12/pcixx12.c (revision 0) +++ southbridge/ti/pcixx12/pcixx12.c (revision 0) @@ -0,0 +1,71 @@

Re: [coreboot] [PATCH] support for two SMSC superios

On Fri, May 14, 2010 at 09:24:29PM +0200, Stefan Reinauer wrote: Index: superio/smsc/fdc37n972/fdc37n972.c === --- superio/smsc/fdc37n972/fdc37n972.c(revision 0) +++ superio/smsc/fdc37n972/fdc37n972.c(revision 0)

Re: [coreboot] [PATCH] Getac P470 notebook support

On Fri, May 14, 2010 at 09:27:46PM +0200, Stefan Reinauer wrote: Add support for the Getac P470 Signed-off-by: Stefan Reinauer ste...@coresystems.de Great, thanks! Acked-by: Uwe Hermann u...@hermann-uwe.de See below for a quick review. Index: mainboard/getac/Kconfig

[coreboot] [commit] r5555 - in trunk/src: mainboard/gigabyte/ga-6bxe superio/ite/it8671f

Author: uwe Date: Fri May 14 23:29:08 2010 New Revision: URL: https://tracker.coreboot.org/trac/coreboot/changeset/ Log: ITE IT8671F: Add it8671f_48mhz_clkin(). This fixes serial console on GIGABYTE GA-6BXE. Signed-off-by: Anders Jenbo and...@jenbo.dk Acked-by: Uwe Hermann

Re: [coreboot] PATCH: IT8671F Select CLKIN

On Sun, May 09, 2010 at 01:49:21AM +0200, Anders Jenbo wrote: +void it8671f_48mhz_clkin(void) Thanks, committed with small changes in r (whee!). /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

Joe, we have visited this type of issue from time to time. The heap size, if it is related to a mainboard (and it is) belongs in the mainboard Kconfig and should not be user-visible. The reason is that if it is visible then that visibility implies that it can be safely changed, much as the baud

Re: [coreboot] [commit] r5525 - in trunk: src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit/be6-ii_v2_0 src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/a

On Wed, May 05, 2010 at 03:12:42PM +0200, repository service wrote: Modified: trunk/src/mainboard/a-trend/atc-6220/devicetree.cb == --- trunk/src/mainboard/a-trend/atc-6220/devicetree.cbWed May 5 14:05:25

Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

Forgive my ignorance, but are there super-compact boards that use this hardware? some kind of low-cost low power thing? Or are there just old systems :-) thanks ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On Fri, May 14, 2010 at 05:38:04PM -0400, ron minnich wrote: Joe, we have visited this type of issue from time to time. The heap size, if it is related to a mainboard (and it is) belongs in the mainboard Kconfig and should not be user-visible. The reason is that if it is visible then that

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On Fri, May 14, 2010 at 7:18 PM, Joe Korty joe.ko...@ccur.com wrote: What failure modes become possible when the heap size is increased? suppose someone for whatever reason sets it to a preposterous size. Not likely but we've seen that sort of thing happen. it's not necessary to have it user

Re: [coreboot] [PATCH] Promote heap sizing to first-class Kconfig citizenship.

On Fri, May 14, 2010 at 05:38:04PM -0400, ron minnich wrote: Joe, we have visited this type of issue from time to time. The heap size, if it is related to a mainboard (and it is) belongs in the mainboard Kconfig and should not be user-visible. The reason is that if it is visible then that

Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this

Mine is an old system, I'm going to use it for serial debugging my desktop machine when I put coreboot there. On May 14, 2010 3:07 PM, ron minnich rminn...@gmail.com wrote: Forgive my ignorance, but are there super-compact boards that use this hardware? some kind of low-cost low power thing?