Stefan Reinauer stefan.reina...@coreboot.org writes:
* Sven Schnelle sv...@stackframe.org [110117 21:46]:
Index: src/ec/acpi/ec.h
===
--- src/ec/acpi/ec.h (revision 0)
+++ src/ec/acpi/ec.h (working copy)
@@ -17,9 +17,11 @@
*
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
pDCTstat-PresetmaxFreq = 800;
}
#171: make error ld.gold.real
---+--
Reporter: rsb@… | Owner: stepan@…
Type: defect |Status: new
Priority: minor | Milestone:
Component: coreboot|
* Bao, Zheng zheng@amd.com [110119 10:37]:
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
static void mctGet_MaxLoadFreq(struct DCTStatStruc
#172: samsung hdd corrupt firmware
---+--
Reporter: rsb@… | Owner: stepan@…
Type: enhancement |Status: new
Priority: major | Milestone:
Component: coreboot|
#172: samsung hdd corrupt firmware
--+--
Reporter: rsb@… | Owner: stepan@…
Type: enhancement|Status: new
Priority: major | Milestone:
Component:
Hi Stefan,
Op woensdag 19 januari 2011 07:56:53 schreef u:
* Nils njaco...@hetnet.nl [110113 15:42]:
Add Geode GX2 memmory descriptors.
Add a simple README file.
Signed-off-by: Nils Jacobs njaco...@hetnet.nl
Thanks, Nils.
Thanks, r6274
Thanks for the review and committing .
But only on the condition that you send a followup patch to change
this option into a choice in the user interface. Please see e.g. how
src/southbridge/via/k8t890/Kconfig implements this. Thanks!
Is the attached patch what you had in mind?
Yup, thanks! r6275
Thanks for the review and
#171: make error ld.gold.real
--+--
Reporter: rsb@… | Owner: stepan@…
Type: defect |Status: closed
Priority: minor | Milestone:
Component: coreboot
#172: samsung hdd corrupt firmware
--+--
Reporter: rsb@… | Owner: stepan@…
Type: enhancement|Status: closed
Priority: major | Milestone:
Component:
Hi Stefan,
Op woensdag 19 januari 2011 07:58:10 schreef u:
Could the problem have anything to do with the fact that the VSA2 code
runs in a different memory region? (setup by oprom)
And therefore the video bars GP, VP and DC are also in a different
address range so VSA2 or VGAbios can
Peter,
you have summed up the challenges of an exhibition/conference very
nicely and I fully agree. My hack room suggestion assumed that there
would be some hack time before booth setup or after teardown, and the
occassional 30-minute hack session, maybe once per day. Leaving one
person alone to
Auf 18.01.2011 02:39, David Hendricks schrieb:
So, I'd like to invite everyone to Google's beautiful campus in Mountain
View for a day of Coreboot hacking, board porting, BIOS flashing, etc. We'll
set a tentative date for Saturday the 29th of this month from noon 'till
8pm. We also have
Hi Fengwei,
I played around with this setup on my Nokia IP530, but could not get it
to work either.
The nokia has no video adaptor, and to me at the time it seems that the
a live CD did
not access the video BIOS 0x10 functions, but uses direct memory
access.
So if you don't have a video
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
It should work. I'm porting the K8V-X SE, and it will boot off CDs, and
get to the point where the kernel puts some debug messages. And this
with some of the configuration still faulty.
The fact that your boot stops may indicate a bug in coreboot,
Hi Marc,
Thank you for your information. If I use PCI video card, it would boot
into linux mint liveCD. But if I do S3 sleep for Linux Mint, it wakeup
with error message from serial port:
Unknown INT10 function 1201!
int10 call returned error.
Best,
Fengwei
On 01/19/2011 05:02 PM, Marc
]HT is initialized to 200MHz. The lspci output (also attached) after
]coreboot loads, shows that 1.6GHz link frequency is possible. The
]documented limit for RS690 is 1GHz. The RS780 code is implemented
]differently, so it has k8 and fam10 support. Do you think it will be
]possible to use
Author: zbao
Date: Thu Jan 20 03:09:24 2011
New Revision: 6276
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6276
Log:
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the
I need to add some functions in early_setup.c of southbridge, sb700, for
example. But some other mainboards don't use those functions. Given the
Werror in Makefile, I can't make these 2 cases pass the compiling both.
What is the resolution? Do I have to add a configuration in mainboard
Kconfig for
Bao, Zheng wrote:
I need to add some functions in early_setup.c of southbridge, sb700, for
example. But some other mainboards don't use those functions. Given the
Werror in Makefile, I can't make these 2 cases pass the compiling both.
You mean to add a function in sb700 early_setup.c that will
Author: zbao
Date: Thu Jan 20 06:41:11 2011
New Revision: 6279
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6279
Log:
Move some board specific functions to sb800.h.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Modified:
I think we need a report table to record the status of every combination
of processor + DIMMs. More test need to be done on the supported boards.
We can not change PresetmaxFreq to 800 until it is ok for each case.
Before that, I am afraid we need to keep in mind that there is a limit
here.
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer zbao checked in revision 6278 to
the coreboot repository. This caused the following
changes:
Change Log:
Features of Bimini board:
RS785
SB800
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Stefan
Author: zbao
Date: Thu Jan 20 06:59:22 2011
New Revision: 6280
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6280
Log:
S3 feanture of SB800. Compiliant with SB700.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Modified:
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer zbao checked in revision 6279 to
the coreboot repository. This caused the following
changes:
Change Log:
Move some board specific functions to sb800.h.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by:
I've got the way to handle it. Thanks.
Zheng
-Original Message-
From: coreboot-boun...@coreboot.org
[mailto:coreboot-boun...@coreboot.org]
On Behalf Of Peter Stuge
Sent: Thursday, January 20, 2011 11:16 AM
To: coreboot@coreboot.org
Subject: Re: [coreboot] what if some mainboard use
Author: zbao
Date: Thu Jan 20 07:28:25 2011
New Revision: 6281
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6281
Log:
Remove the code for debugging.
Signed-off-by: Zheng Bao zheng@amd.com
Acked-by: Zheng Bao zheng@amd.com
Modified:
27 matches
Mail list logo
