Hi,
Can we have it via weak function and mainboard.c callback as I changed this in
SB700? So future boards can set it up too.
Thanks,
Rudolf
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I've compiled support for the Siemens 'sitemp' Mainboard. The board is similar
to the AMD dbm690t.
I adapt the code from dbm690t according to customer requirement specification.
Linux is booting with seabios/filo.
Windows XP is booting with seabios.
This board comes with two hardware variants so
Am Dienstag, den 25.01.2011, 10:44 + schrieb Joseph Kellermann:
> Also I've found an issue:
> The default 'pci_set_subsystem' sets the subvendor/device id register#
> 0x2c. However, for a few devices in the RS690 the register is 0x4c
> respectively 0x50.
>
> Moved 'pci_set_subsystem' to a wea
> couldn't you just modify the chipset
> drivers to point to a different set_subsystem implementation where
> necessary?
Yes, I can do, but how can I implement these requirement:
> board comes with two hardware variants so I have to set up subvendor/device
> ids accordingly.
that's, in 'mainboard
Am Dienstag, den 25.01.2011, 12:03 + schrieb Joseph Kellermann:
> Yes, I can do, but how can I implement these requirement:
> > board comes with two hardware variants so I have to set up subvendor/device
> > ids accordingly.
> that's, in 'mainboard.c' I check for 'PLX device present' and set u
Hi List,
Can somebody please comment on the patch below? Would be nice as this
patch is required for the upcoming Thinkpad Patch Series.
Cheers,
Sven.
Sven Schnelle writes:
> Stefan Reinauer writes:
>
>> * Sven Schnelle [110117 21:46]:
>>> Index: src/ec/acpi/ec.h
>>> ===
Am Dienstag, den 25.01.2011, 13:24 +0100 schrieb Georgi, Patrick:
> I'm not quite sure if using weak functions to wrap the subsystem
> CONFIG_* values is actually the right approach, I'll work on a patch to
> discuss.
Here it is.
I tested it by providing a mainboard_pci_subsystem_vendor_id for my
b
Great, i will test it.
Thanks,
Joseph
Von: Georgi, Patrick [patrick.geo...@secunet.com]
Gesendet: Dienstag, 25. Januar 2011 13:54
Bis: Joseph Kellermann
Cc: coreboot@coreboot.org
Betreff: Re: [coreboot] Moved 'pci_set_subsystem' to a weak function: Support
Ok, it works.
I will provide patches for the RS690 device specific register.
Regards,
Joseph
Von: Georgi, Patrick [patrick.geo...@secunet.com]
Gesendet: Dienstag, 25. Januar 2011 13:54
Bis: Joseph Kellermann
Cc: coreboot@coreboot.org
Betreff: Re: [coreboo
This patch fixes a potential system hang (see 'Revision Guide for AMD NPT
Family 0Fh Processors' 33610.pdf).
Signed-off-by: Josef Kellermann
**
IMPORTANT NOTICE / WICHTIGER HINWEIS
This communication c
Stefan Reinauer wrote:
> > Can I ask why you don't want to create a commit for the changes?
>
> It needs more of git setup in order to use the system (such as the user
> name and email),
That's a point, though it doesn't matter significantly because the
commit would not really be sent to anyone e
Hi,
been thinking about our use of CMOS for configuration lately, and
finally came up with a scheme that might just work out.
Currently, the CMOS layout is defined per-board making it cumbersome to
add new fields for chipset drivers (you have to update all boards that
use the component and CMOS,
Author: stepan
Date: Tue Jan 25 20:27:23 2011
New Revision: 6298
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6298
Log:
Fix abuild
thanks to Kevin who came up with this
Signed-off-by: Stefan Reinauer
Acked-by: Stefan Reinauer
Modified:
trunk/payloads/external/SeaBIOS/Makefile.
Hi all,
Attached patch adds support for CMOS options which can alter DDR Memory, HT GPU,
and Sideport Voltages. Also as a quick hack it can change CPU base frequency
from 200MHz to something else.
I think this would be nice to show on FOSDEM.It could be extended so not only
CPU PLL is progra
Hello,
While hunting yet another bug, I noticed that part of my serial log is missing.
Especially I missed the Allocating & Setting resources.
It turns out that the code which enables specific LDN is somewhat buggy:
static void w83627dhg_pnp_enable(device_t dev)
{
- if (!dev->enable
* Georgi, Patrick [110125 08:59]:
> Hi,
>
> attached patch adds a new CMOS variable which triggers activation of the
> LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the
> variable reset, it's not.
>
> There's probably a better place for the code to end up in, but this has
>
* repository service [110125 20:27]:
> Author: stepan
> Date: Tue Jan 25 20:27:23 2011
> New Revision: 6298
> URL: https://tracker.coreboot.org/trac/coreboot/changeset/6298
>
> Log:
> Fix abuild
>
> thanks to Kevin who came up with this
Not this is just to get this working. I think we should st
Nice work, Rudolf!
> Index: src/mainboard/asrock/939a785gmh/romstage.c
> ===
> --- src/mainboard/asrock/939a785gmh/romstage.c(revision 6298)
> +++ src/mainboard/asrock/939a785gmh/romstage.c(working copy)
> @@ -48,6 +4
Hello,
Attached patch fixes the LPC decode ranges of SB700. We enable early only
Serial/SIO/RTC. Everything else needs to be done by lpc.c Problem was that early
settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 et
Hi,
I think now it matches the old values (minus the MEM voltage which seems to be
higher when set to "auto" in Asrock BIOS)
+ /* remap to match the bit meanings */
+ mem_volt = 7 - mem_volt;
+ ht_volt = !ht_volt;
+ sideport_volt = !sideport_volt;
+ gpu_volt = 7 -
Hi,
Btw we have a problem this W83527HG has exactly same ID as mine W83627DHG-P
id=0xb0, rev=0x73
And my chip does have a serial paralell spi etc... What now? Looks like it may
be some shrunk package maybe only?
Maybe we can add SPI/COM1/COM2 LDN as it has the classic old W83627DHG (0xa02)
* Rudolf Marek [110126 00:01]:
> Hello,
>
> Attached patch fixes the LPC decode ranges of SB700. We enable early
> only Serial/SIO/RTC. Everything else needs to be done by lpc.c
> Problem was that early settings survived, because the lpc.c is doing
> ORs only...
> Hence we decode quite a lot and
Hi,
how can I enable the cmos recovery feature and where I have to put the
cmos.default file ?
In my local version I have added
##
if [ -f $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.default ]; \
then \
$(CBFSTO
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