Author: oxygene
Date: Thu Feb 10 09:49:57 2011
New Revision: 6341
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6341
Log:
RS690: Provide support for MMCONF.
If enabled, set up 0xe000..0xf000 as MMCONF
area. Must still be configured in per-board ACPI for
the OS to pick it up,
On 08/02/2011 01:38, Jonathan A. Kollasch wrote:
Hi,
I noticed that, other than initialization in almost every superio, the
'set' member of struct io_info doesn't seem to be referenced by the pnp
code. Worth the removing?
Jonathan Kollasch
I found the same thing as you a while ago.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello everybody,
I would like to start with thanking all volunteers on the coreboot
project! At FOSDEM 2011 I had dinner with two of the volunteers. I have
been watching the coreboot for the past years, as something that I love
to have running on my
According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for
On Thu, Feb 10, 2011 at 12:32 PM, Scott Duplichan sc...@notabs.org wrote:
According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem
Author: sduplichan
Date: Thu Feb 10 21:49:56 2011
New Revision: 6342
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6342
Log:
According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance
inteltool: first preview for machine-readable output
Signed-off-by: Anton Kochkov anton.koch...@gmail.com
---
This is only for preview and discussion, it's still ugly and dont safe/clear.
inteltool_machine_readable_first_preview.patch
Description: Binary data
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coreboot mailing list:
* Mark Marshall mark.marsh...@csr.com [110210 11:52]:
I found the same thing as you a while ago. The io_info structure in
pnp.h is never referenced by the code, and it's purpose is never
really defined anywhere. If you change the name to something else
(just in the header file) the code
* Peter Stuge pe...@stuge.se [110209 20:44]:
I checked the content of build/coreboot.rom and the last byte was
0x0a!! Which is written probably on the top of our EEPROM. Right?
but src/arch/i386/init/ldscript.ld specifies the last byte as 0x00!!
SECTIONS {
_ROMTOP = 0xfff0;
inteltool: first preview for machine-readable output
Signed-off-by: Anton Kochkov anton.koch...@gmail.com
---
This is only for preview and discussion, it's still ugly and dont safe/clear.
inteltool_machine_readable_first_preview.patch
Description: Binary data
#include stdio.h
#include
inteltool: first preview for machine-readable output, fixes
Signed-off-by: Anton Kochkov anton.koch...@gmail.com
---
This is only for preview and discussion, it's still ugly and dont safe/clear.
inteltool_machine_readable_second_preview.patch
Description: Binary data
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