[coreboot] [PATCH v3] Lenovo X60s Support

Hi List, this patch adds support for Lenovo X60s (Model 1703) Thinkpads. It is a basic Patch without SMI and ACPI, as this makes it probably easier to review. I'll send SMI and ACPI Patches as soon as the patch is commited. Signed-off-by: Sven Schnelle Index: src/mainboard/Kconfig =

[coreboot] [PATCH v4] Lenovo X60s support

Hi List, next version of my patch because: - re-add old Copyright to copied files - add small GPIO description (not proven to be correct, and the actual register values are still taken from vendors settings) Index: src/mainboard/Kconfig ===

[coreboot] Trac reminder: list of new ticket(s)

Ticket Owner Status Description #174 ste...@coresystems.de new Unable to boot from qemu-kvm -- seems to be a cbfs problem #170 ste...@coresystems.de new Need coreboot for ASUS P4PE_X/SE #169 ste...@coresystems.de ne

[coreboot] patch for errata#169

this patch should be applied to k8_f0 (NODE_HT(x)), not k8_f3 (NODE_MC(x)). see patch for details. Signed-off-by: Josef Kellermann diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 12c125c..f66e2cf 100644 --- a/src/nor

[coreboot] amd/rs690/gfx.c cleanup

removed /* LPC DMA Deadlock workaround? */ ... setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in amdk8/coherent.c see patch for details. Signed-off-by: Josef Kellermann diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/

Re: [coreboot] amd/rs690/gfx.c cleanup

On 02/14/2011 06:07 PM, Josef Kellermann wrote: > removed /* LPC DMA Deadlock workaround? */ ... > > setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in > amdk8/coherent.c > > see patch for details. > > Signed-off-by: Josef Kellermann > WOW! Nice

Re: [coreboot] patch for errata#169

On 02/14/2011 05:17 PM, Josef Kellermann wrote: > this patch should be applied to k8_f0 (NODE_HT(x)), not k8_f3 (NODE_MC(x)). > see patch for details. > > Signed-off-by: Josef Kellermann > You are correct. This is what happens when writing patches at 2AM. I'm glad you c

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.

On Sun, Feb 13, 2011 at 2:43 PM, Vibrans, Frank wrote: > Add AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8. > > This code currently generates many warnings that are functionally benign.   > These are > being addressed, but the wheels of bureaucracy turn slowly.  This drop > supports AMD > cpu

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.

Hi! Thank you very much, Frank, Gary, Kenneth, Kerry, Kevin, Michael, Mike and Zheng! And of course all the others that were involved! This is great moment for coreboot, and we are all incredibly excited about this! Those among the coreboot community that have done hardware ports before can estim

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.

* Vibrans, Frank [110213 22:43]: > Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8. > > This code currently generates many warnings that are functionally benign. > These are > being addressed, but the wheels of bureaucracy turn slowly. This drop > supports AMD > cpu families 10h and 14h.

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 2 of 8

* Vibrans, Frank [110213 22:47]: > Add AMD Agesa northbridge wrapper code. Patch 2 of 8. > > This code provides cpu northbridge initialization for Family 14h cpus. It is > dependent on the AMD Agesa code. > > Signed-off-by Frank Vibrans Acked-by: Stefan Reinauer -- coreboot mailing list

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 3 of 8.

* Vibrans, Frank [110213 22:49]: > Add AMD CIMx SB800 wrapper code. Patch 3 of 8. > > This code provides southbridge initialization for SB800 south bridges. It is > dependent on the AMD CIMx/SB800 code. > > Signed-off-by Frank Vibrans Acked-by: Stefan Reinauer -- coreboot mailing list: c

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 4 of 8.

* Vibrans, Frank [110213 22:50]: > Add AMD cpu wrapper code. Patch 4 of 8. > > This code provides cpu early initialization for Family 14h cpus. It is > dependent on the AMD Agesa code. > > Signed-off-by Frank Vibrans > > Add AMD cpu wrapper code. Patch 4 of 8. > > This code provides cpu e

Re: [coreboot] (no subject)

* Vibrans, Frank [110213 22:52]: > Add support for AMD Agesa wrapper code. Patch 5 of 8. > > This code fixes a number of build issues related to the AMD Agesa code. > The particular issues are global variables existing in romstage and the > use of GCC intrinsics in the build. The former issue w

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 6 of 8.

* Vibrans, Frank [110213 22:53]: > Add Fintek f81865f superio code. Patch 6 of 8. > > This code provides support for the superio chip on the IBASE Technology > DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD > code. > > Signed-off-by Frank Vibrans Acked-by: Stefan Rei

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 7 of 8.

* Vibrans, Frank [110213 22:55]: > Add SMSC KBC 1100 superio code. Patch 7 of 8. > > This code provides support for the superio chip on the AMD Inagua > platform (not commercially available). It is independent of the AMD > code. > > Signed-off-by Frank Vibrans Acked-by: Stefan Reinauer --

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 8 of 8.

* Vibrans, Frank [110213 22:55]: > Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. > > This code provides support for IBASE Technology DB-FT1 (AMD code > name Persimmon) and AMD Inagua platforms. It is dependent on all > other patches in this set. > > Signed-off-by Frank Vibrans

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.

On Mon, Feb 14, 2011 at 11:07 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:43]: >> Add AMD Agesa and AMD CIMx SB800 code.  Patch 1 of 8. >> >> This code currently generates many warnings that are functionally benign.   >> These are >> being addressed, but the wheels of bureaucracy tur

[coreboot] [commit] r6345 - in trunk/src/northbridge/amd: . agesa_wrapper agesa_wrapper/family14 agesa_wrapper/family14/root_complex

Author: mjones Date: Mon Feb 14 19:35:15 2011 New Revision: 6345 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6345 Log: This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code. Signed-off-by: Frank Vibrans Acked-by: Stefan Reinau

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 2 of 8

On Mon, Feb 14, 2011 at 11:07 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:47]: >> Add AMD Agesa northbridge wrapper code.  Patch 2 of 8. >> >> This code provides cpu northbridge initialization for Family 14h cpus.  It is >> dependent on the AMD Agesa code. >> >> Signed-off-by Frank V

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 3 of 8.

On Mon, Feb 14, 2011 at 11:07 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:49]: >> Add AMD CIMx SB800 wrapper code.  Patch 3 of 8. >> >> This code provides southbridge initialization for SB800 south bridges.  It is >> dependent on the AMD CIMx/SB800 code. >> >> Signed-off-by Frank Vib

[coreboot] [commit] r6347 - in trunk/src/cpu/amd: . agesa_wrapper agesa_wrapper/family14

Author: mjones Date: Mon Feb 14 19:42:12 2011 New Revision: 6347 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6347 Log: Add AMD cpu wrapper code. Patch 4 of 8. This code provides cpu early initialization for Family 14h cpus. It is dependent on the AMD Agesa code. Signed-off-by: Fra

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 4 of 8.

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:50]: >> Add AMD cpu wrapper code.  Patch 4 of 8. >> >> This code provides cpu early initialization for Family 14h cpus.  It is >> dependent on the AMD Agesa code. >> >> Signed-off-by Frank Vibrans >> > >> Add

[coreboot] [commit] r6348 - in trunk: . src/arch/x86/init

Author: mjones Date: Mon Feb 14 19:47:37 2011 New Revision: 6348 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6348 Log: This code fixes a number of build issues related to the AMD Agesa code. The particular issues are global variables existing in romstage and the use of GCC intrinsi

Re: [coreboot] (no subject)

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:52]: >> Add support for AMD Agesa wrapper code.  Patch 5 of 8. >> >> This code fixes a number of build issues related to the AMD Agesa code. >> The particular issues are global variables existing in romstage an

[coreboot] [commit] r6349 - in trunk/src/superio/fintek: . f81865f

Author: mjones Date: Mon Feb 14 19:52:15 2011 New Revision: 6349 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6349 Log: This code provides support for the superio chip on the IBASE Technology DB-FT1 (AMD code name Persimmon) platform. It is independent of the AMD code. Signed-off-b

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 6 of 8.

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:53]: >> Add Fintek f81865f superio code.  Patch 6 of 8. >> >> This code provides support for the superio chip on the IBASE Technology >> DB-FT1 (AMD code name Persimmon) platform.  It is independent of the AMD

[coreboot] [commit] r6350 - trunk/src/include/cpu/amd

Author: mjones Date: Mon Feb 14 19:56:10 2011 New Revision: 6350 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6350 Log: I missed a file that was part of the AMD AGESA CPU wrapper checkin, r6347. Signed-off-by: Frank Vibrans Acked-by: Marc Jones + +#define HWCR_MSR

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 4 of 8.

On Mon, Feb 14, 2011 at 11:42 AM, Marc Jones wrote: > On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer > wrote: >> * Vibrans, Frank [110213 22:50]: >>> Add AMD cpu wrapper code.  Patch 4 of 8. >>> >>> This code provides cpu early initialization for Family 14h cpus.  It is >>> dependent on the A

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 6 of 8.

On Mon, Feb 14, 2011 at 11:52 AM, Marc Jones wrote: > On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer > wrote: >> * Vibrans, Frank [110213 22:53]: >>> Add Fintek f81865f superio code.  Patch 6 of 8. >>> >>> This code provides support for the superio chip on the IBASE Technology >>> DB-FT1 (AMD

[coreboot] [commit] r6351 - in trunk/src/superio/smsc: . kbc1100

Author: mjones Date: Mon Feb 14 20:00:13 2011 New Revision: 6351 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6351 Log: This code provides support for the superio chip on the AMD Inagua platform (not commercially available). It is independent of the AMD>code. Signed-off-by: Frank Vi

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 7 of 8.

On Mon, Feb 14, 2011 at 11:08 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:55]: >> Add SMSC KBC 1100 superio code.  Patch 7 of 8. >> >> This code provides support for the superio chip on the AMD Inagua >> platform (not commercially available).  It is independent of the AMD >> code. >>

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 8 of 8.

On Mon, Feb 14, 2011 at 11:09 AM, Stefan Reinauer wrote: > * Vibrans, Frank [110213 22:55]: >> Add IBASE DB-FT1 and AMD Inagua motherboards.  Patch 8 of 8. >> >> This code provides support for IBASE Technology DB-FT1 (AMD code >> name Persimmon) and AMD Inagua platforms.  It is dependent on all >

[coreboot] [commit] r6353 - trunk/src/mainboard/amd/inagua

Author: oxygene Date: Mon Feb 14 20:15:36 2011 New Revision: 6353 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6353 Log: Fix Typo. (and why is that file, and some of its siblings per-board?) Signed-off-by: Patrick Georgi Acked-by: Patrick Georgi Modified: trunk/src/mainboard/am

[coreboot] [commit] r6354 - trunk/src/southbridge/amd/rs690

Author: oxygene Date: Mon Feb 14 20:19:58 2011 New Revision: 6354 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6354 Log: Removed LPC DMA Deadlock workaround... Setting bit#21 in k8_f0#68 is part of the errata#169 which is handled in amdk8/coherent.c Signed-off-by: Josef Kellermann

[coreboot] [commit] r6355 - trunk/src/northbridge/amd/amdk8

Author: oxygene Date: Mon Feb 14 20:21:28 2011 New Revision: 6355 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6355 Log: Errata #169 works on HT, not MC Signed-off-by: Josef Kellermann Acked-by: Alexandru Gagniuc Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c Modified

[coreboot] [commit] r6356 - in trunk/payloads/libpayload/include: . arpa

Author: oxygene Date: Mon Feb 14 20:23:33 2011 New Revision: 6356 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6356 Log: Some more POSIX compatibility - Add assert.h - Add arpa/inet.h - Add assert macro Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Added: trunk/paylo

[coreboot] [commit] r6357 - trunk/payloads/libpayload/bin

Author: oxygene Date: Mon Feb 14 20:24:37 2011 New Revision: 6357 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6357 Log: lpgcc was too noisy in some cases Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Modified: trunk/payloads/libpayload/bin/lpgcc Modified: trunk/payl

[coreboot] [commit] r6358 - in trunk/payloads/libpayload: include libc

Author: oxygene Date: Mon Feb 14 20:25:27 2011 New Revision: 6358 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6358 Log: Stub out FILE*, stdout/stdin/stderr and implement fprintf on these - Add FILE* - Add stdout, stdin, stderr stubs - Add fprintf that redirects to printf for stdout

[coreboot] [commit] r6359 - in trunk/payloads/libpayload: include libc

Author: oxygene Date: Mon Feb 14 20:26:22 2011 New Revision: 6359 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6359 Log: Use fprintf(stderr, ...) in library Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Modified: trunk/payloads/libpayload/include/assert.h trunk/pay

[coreboot] [commit] r6360 - in trunk/src/mainboard: . lenovo lenovo/x60

Author: stuge Date: Mon Feb 14 21:02:47 2011 New Revision: 6360 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6360 Log: Lenovo ThinkPad X60 / X60s Support Adds support for Lenovo X60 series ThinkPads. So far, only X60s (Model 1703) has been tested. It's a basic patch without SMI and

Re: [coreboot] [PATCH v4] Lenovo X60s support

Sven Schnelle wrote: > Hi List, > > next version of my patch because: > > - re-add old Copyright to copied files > - add small GPIO description (not proven to be correct, > and the actual register values are still taken from vendors > settings) Acked-by: Peter Stuge r6360 pgpPSmk1vtSJS.p

[coreboot] msrtool: generation from C code to XML

msrtool: add support for producing xml files from C code Signed-off-by: Anton Kochkov --- export_msr.patch Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] superiotool: generation from C code to XML

superiotool: add support for producing xml files from C code Signed-off-by: Anton Kochkov --- export_sio.patch Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] AMD Agesa and AMD CIMx SB800 code. Patch 3 of 8.

Hi Frank, case 0: + //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata + break; I think I know why. Most likely the wideIO port is too wide. I created some patches recently to fix it in sb700 code + sb800 and sb600. http://tracke

[coreboot] build service results for r6357

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6357 to the coreboot repository. This caused the following changes: Change Log: lpgcc was too noisy in some cases Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Build

[coreboot] Free (possibly recoverable?) Gigabyte GA-MA785GMT-UD2H

Hello all, I recently made my first attempt at installing coreboot. I happened to mess up. While trying to jump across the appropriate pins to engage DualBIOS recovery, my jumper slipped and I shorted out. The mainboard is not completely broken. It succeeds at progressing to the point where th

Re: [coreboot] superiotool: generation from C code to XML

* Антон Кочков [110214 22:02]: > superiotool: add support for producing xml files from C code > > Signed-off-by: Anton Kochkov Is it possible to make superiotool read those instead of the C structures as its database? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/m

[coreboot] build service results for r6358

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6358 to the coreboot repository. This caused the following changes: Change Log: Stub out FILE*, stdout/stdin/stderr and implement fprintf on these - Add FILE* - Add stdout, stdin,

[coreboot] [commit] r6361 - trunk/payloads/external/SeaBIOS

Author: stepan Date: Tue Feb 15 01:14:32 2011 New Revision: 6361 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6361 Log: use git.seabios.org for checking out seabios. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/payloads/external/SeaBIOS/Makefile.inc

[coreboot] [commit] r6362 - trunk/src/southbridge/amd/cimx_wrapper/sb800

Author: stepan Date: Tue Feb 15 01:23:05 2011 New Revision: 6362 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6362 Log: SERIAL_POST was renamed to CONSOLE_POST a while ago Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/southbridge/amd/cimx_wrapper/s

[coreboot] [commit] r6363 - trunk/src/mainboard/amd/inagua

Author: mjones Date: Tue Feb 15 01:27:24 2011 New Revision: 6363 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6363 Log: Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be addded by the developer if needed. Fixes abuild issues. Signed-off-by: Marc Jones Ac

Re: [coreboot] build service results for r6357

On Mon, Feb 14, 2011 at 4:45 PM, repository service wrote: > Dear coreboot readers! > > This is the automatic build system of coreboot. > > The developer "oxygene" checked in revision 6357 to > the coreboot repository. This caused the following > changes: > > Change Log: > lpgcc was too noisy in s

[coreboot] build service results for r6359

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6359 to the coreboot repository. This caused the following changes: Change Log: Use fprintf(stderr, ...) in library Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Bui

[coreboot] build service results for r6352

Dear coreboot readers! This is the automatic build system of coreboot. The developer "mjones" checked in revision 6352 to the coreboot repository. This caused the following changes: Change Log: Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8. This code provides support for IBASE Tec

[coreboot] build service results for r6353

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6353 to the coreboot repository. This caused the following changes: Change Log: Fix Typo. (and why is that file, and some of its siblings per-board?) Signed-off-by: Patrick Georgi

[coreboot] build service results for r6355

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6355 to the coreboot repository. This caused the following changes: Change Log: Errata #169 works on HT, not MC Signed-off-by: Josef Kellermann Acked-by: Alexandru Gagniuc Bui

[coreboot] build service results for r6362

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6362 to the coreboot repository. This caused the following changes: Change Log: SERIAL_POST was renamed to CONSOLE_POST a while ago Signed-off-by: Stefan Reinauer Acked-by: Stefan