On 02/24/2011 04:14 AM, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
board. Raminit seems to go okay, as does the first bits of ramstage.
However, ramstage fails after the first two passes through
rs780_enable(). It stalls in
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6378 to
the coreboot repository. This caused the following
changes:
Change Log:
Tyan/s2735 doesn't need to define its own hard_reset function anymore.
The southbridge already
On 02/23/2011 03:51 PM, Xavi Drudis Ferran wrote:
Pompous ?
Yes. This is an option for experienced users, and people too smart for
they own sake (pozitive connotation), that value their freedom more than
practicality. They will go to an extra effort to ensure that. Therefore,
considering the
Alex G. wrote:
Is the 'adding a line in Kconfig' option hassle free enough for you?
I just don't see a way to make it obscure enough it menuconfig, but I
won't object if you do find one.
Don't we have an experts option that will enable further options?
//Peter
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coreboot mailing list:
Dear Jonathan,
Am Donnerstag, den 24.02.2011, 02:14 + schrieb Jonathan A. Kollasch:
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
board.
what is the model number?
[…]
Good luck with the port!
Thanks,
Paul
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Description: This is a digitally signed
Am Donnerstag, den 24.02.2011, 05:34 +0100 schrieb Peter Stuge:
Scott Duplichan wrote:
These are really great news.
[…]
This looks like a nice board for a media center system.
Indeed. There are some reviews available of this board [1][2].
Unfortunately in Germany all the online shops seem
Hello everybody,
I bought a new ASUSTeK M4A87TD/USB3 motherboard and discussed it on irc
#coreboot, there is a developer with the same motherboard.
I know got these motherboards that need features provided by coreboot:
1x ASUSTeK M4A87TD/USB3 [1] (AMD 870/SB850)
1x Gigabyte GA-890GPA-UD3H [2]
Dear coreboot community,
it is really amazing what happened in the last years and especially in
the last months. A lot of people came – for me – out of nowhere and did
great contributions. Also AMD did great with their latest contributions
[1].
Today, Scott sent a patch to the list to support
Am Donnerstag, den 17.02.2011, 07:35 +0100 schrieb xdrudis:
see patch
Any opinion on these patches? Patch 1-8 seem to be refactorings only,
and splitting functions into smaller logical units looks good to me, but
I'd like to hear from someone deeper in the AMD code.
Patrick
--
Patrick Georgi
Author: oxygene
Date: Thu Feb 24 14:54:10 2011
New Revision: 6379
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6379
Log:
Add new option 'sata_mode' to CMOS and 'SATA_MODE' to Kconfig for AMD SB600
coreboot used to set the chipset to IDE mode unconditionally.
Now, the user has a
Hi Josef.
Thank you for the contribution.
Am Freitag, den 18.02.2011, 20:12 +0100 schrieb Josef Kellermann:
Attached patch implements a new CMOS option 'sata_mode'.
A new Kconfig option 'SATA_MODE' with default 'ide' is added to
amd/sb600/Kconfig.
I changed the Kconfig handling a bit to not
Ping!
Alex
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On Thu, Feb 24, 2011 at 02:14:07AM +, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
board. Raminit seems to go okay, as does the first bits of ramstage.
However, ramstage fails after the first two passes through
rs780_enable(). It
Author: oxygene
Date: Thu Feb 24 15:35:42 2011
New Revision: 6380
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6380
Log:
Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS
This affects the CMOS options iommu, ECC_memory, max_mem_clock,
hw_scrubber,
Am Freitag, den 18.02.2011, 20:24 +0100 schrieb Josef Kellermann:
Attached patch adds sane compile-time defaults via Kconfig options for
CMOS options 'iommu, ECC_memory, max_mem_clock, hw_scrubber,
I changed the ramstage code a bit.
The romstage code could and should also be very different (all
Dear coreboot readers!
This is the automatic build system of coreboot.
The developer oxygene checked in revision 6380 to
the coreboot repository. This caused the following
changes:
Change Log:
Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS
This affects the
Hi Paul,
On Thu, Feb 24, 2011 at 6:18 AM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear coreboot community,
it is really amazing what happened in the last years and especially in
the last months. A lot of people came – for me – out of nowhere and did
great contributions. Also
On Thu, Feb 24, 2011 at 7:23 AM, Jonathan A. Kollasch
jakll...@kollasch.net wrote:
On Thu, Feb 24, 2011 at 02:14:07AM +, Jonathan A. Kollasch wrote:
Hi,
I've attempted to use the rs780 and sb800 code on a AM3 870 + SB850
board. Raminit seems to go okay, as does the first bits of
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Marc Jones
Sent: Thursday, February 24, 2011 10:45 AM
To: Jonathan A. Kollasch
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] 870 attempt
On Thu, Feb 24, 2011 at 7:23 AM,
Peter wrote:
]Scott Duplichan wrote:
] I accidentally did the 'svn cp' step interactively instead of by
] patch. The attached patch completes the work of converting AMD
] Persimmon into ASRock E350M1.
]
]Good stuff. Some simple comments, then I'll ack.
]
] A video option rom needs to be added to
On Thu, Feb 24, 2011 at 6:31 AM, Georgi, Patrick
patrick.geo...@secunet.com wrote:
Am Donnerstag, den 17.02.2011, 07:35 +0100 schrieb xdrudis:
see patch
Any opinion on these patches? Patch 1-8 seem to be refactorings only,
and splitting functions into smaller logical units looks good to me,
Scott Duplichan wrote:
] A video option rom needs to be added to support the built-in uma
] graphics.
]
]Does the default filename match what was extracted from factory EFI?
I do not know of a way to recover the original filename of the
extracted video BIOS. After booting the factory BIOS,
On Thu, Feb 24, 2011 at 11:07:04AM -0600, Scott Duplichan wrote:
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Marc Jones
Sent: Thursday, February 24, 2011 10:45 AM
To: Jonathan A. Kollasch
Cc: coreboot@coreboot.org
Peter wrote:
]Scott Duplichan wrote:
] ] A video option rom needs to be added to support the built-in uma
] ] graphics.
] ]
] ]Does the default filename match what was extracted from factory EFI?
]
] I do not know of a way to recover the original filename of the
] extracted video BIOS. After
* repository service s...@coreboot.org [110224 08:43]:
Author: oxygene
Date: Thu Feb 24 08:43:37 2011
New Revision: 6378
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6378
Log:
Tyan/s2735 doesn't need to define its own hard_reset function anymore.
The southbridge already
* repository service s...@coreboot.org [110224 15:35]:
Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c
==
--- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Thu Feb 24 14:54:10
2011(r6379)
+++
* Rudolf Marek r.ma...@assembler.cz [110224 21:04]:
Hi all
Attaching update patch. Not much changed, only comments added.
It adds support for automatic PSS object generation for AMD pre fam
Fh CPU. Those CPUs require a hardcoded table, which I managed to
rewrite during one particularly
On Thu, Feb 24, 2011 at 02:31:29PM +0100, Georgi, Patrick wrote:
Am Donnerstag, den 17.02.2011, 07:35 +0100 schrieb xdrudis:
see patch
Any opinion on these patches? Patch 1-8 seem to be refactorings only,
and splitting functions into smaller logical units looks good to me, but
I'd like to
* Scott Duplichan sc...@notabs.org [110224 05:03]:
The attached patch gets coreboot going on the ASRock E350M1 board.
This is an AMD family 14h Fusion board I bought for US $120, including
processor. The video option rom is from the supplied UEFI BIOS.
The patch modifies the persimmon
Any chance to move the SSDTs to the northbridge/southbridge/cpu
directory instead of having them live under mainboard?
* Scott Duplichan sc...@notabs.org [110224 07:05]:
Index: src/mainboard/asrock/e350m1/acpi/ssdt2.asl
===
---
* Scott Duplichan sc...@notabs.org [110224 18:07]:
-Original Message-
From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On
Behalf Of Marc Jones
Sent: Thursday, February 24, 2011 10:45 AM
To: Jonathan A. Kollasch
Cc: coreboot@coreboot.org
Subject: Re:
* Georgi, Patrick patrick.geo...@secunet.com [110222 15:35]:
Am Donnerstag, den 17.02.2011, 20:05 +0100 schrieb Stefan Reinauer:
I agree we want this, though. Can you please put Makefile.inc in src/?
We currently have subdirs-y = ... util/cbfstool in there. That would be
++ugly with
Stefan Reinauer wrote:
] +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
]if CONFIG_SIO_PORT is defined in Kconfig (why?) we could as well use it
]in romstage.c. Is there a chance to remove it from Kconfig instead?
Certainly the two occurrences of 2e is not ideal. This change works:
-#define
Stefan Reinauer wrote:
]Any chance to move the SSDTs to the northbridge/southbridge/cpu
]directory instead of having them live under mainboard?
It looks like SSDT2,3,4,5 are never used and can be removed from
this project.
Thanks,
Scott {
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coreboot mailing list: coreboot@coreboot.org
When using Artec loader and no file system, use dev_name for initrd
instead of flashb.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: fs/filesys.h
===
--- fs/filesys.h(revision 140)
+++ fs/filesys.h
load_linux_kernel() checks using_devsize, so we need to
clear it if we are using Artec loader without a file
system.
Signed-off-by: Nathan Williams nat...@traverse.com.au
Index: i386/artecboot.c
===
--- i386/artecboot.c(revision
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