[coreboot] [PATCH] simplify coreboot console.h

See patch. Simplify coreboot's console/console.h - shift most (romcc) code out of console.h into arch/x86/lib/romcc_console.c - rename arch/x86/lib/printk_init.c to .../romstage_console.c - drop FUNCTIONS_FOR_PRINT since __console_tx_* are already functions, so there should not be any side effe

Re: [coreboot] Intel 82541pi network card does not work on ASUS M2V-MX SE

I see. Thanks. I will try it tomorrow. Regards, Jiang On Tue, Apr 19, 2011 at 9:15 PM, Stefan Reinauer wrote: > * Jiang Wang [110419 23:56]: >> Hi, >> >> I tried to use an external PCI network card ( 8254pi) with m2v-mx se >> mother board. However, the booting process hangs. On the screen, it

Re: [coreboot] [PATCH 4/4] pci1x2x: use cardbus_read_resources()/cardbus_enable_resources()

* Sven Schnelle [110419 21:47]: > Signed-off-by: Sven Schnelle What's the difference? Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH 3/4] pci1x2x: use pci_ops set_subsystem instead of custom code

* Sven Schnelle [110419 21:47]: > Signed-off-by: Sven Schnelle Will that also need a change in the nokia IP530 board's devicetree.cb? Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] build service results for r6522

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6522 to the coreboot repository. This caused the following changes: Change Log: fix boards that still had some uart init remainders Signed-off-by: Stefan Reinauer Acked-by: Stefan

Re: [coreboot] [PATCH 2/4] pci1x2x: add PCI1510 device IDs

* Sven Schnelle [110419 21:47]: > Signed-off-by: Sven Schnelle Acked-by: Stefan Reinauer -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH 1/4] pci1x2x: use devicetree register configuration

* Sven Schnelle [110419 21:47]: > Signed-off-by: Sven Schnelle > static void ti_pci1x2y_init(struct device *dev) > { > + > printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus > controller\n"); > + struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; You sh

Re: [coreboot] Dell Latitude D820

* Philippe LeCavalier [110419 20:22]: > Hi All. > > Just joined the list to find out your opinion on whether or not I should > put coreboot on my laptop. > > First off, what do I gain? I read it's faster but I don't really think > my BIOS is slow. OR is it? Perhaps seeing is believing... If you

Re: [coreboot] Failed to launch windows 7 and two more questions ...

* Boris Shpoungin [110419 23:31]: > Could you recommend any manual which describe coreboot porting process to new > not supported platform? Does it exist at all? The Wiki is an excellent source of information. > Could you provide rough effort estimate to port coreboot to new unsupported > plat

Re: [coreboot] Intel 82541pi network card does not work on ASUS M2V-MX SE

* Jiang Wang [110419 23:56]: > Hi, > > I tried to use an external PCI network card ( 8254pi) with m2v-mx se > mother board. However, the booting process hangs. On the screen, it > shows, "Chrome VGA textmode initialized", and stops there. > > The serial console output is attached. Is this the N

[coreboot] [commit] r6523 - in trunk/src: include lib southbridge/via/vt82c686

Author: stepan Date: Wed Apr 20 03:08:25 2011 New Revision: 6523 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6523 Log: drop dead uart init code. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/include/uart8250.h trunk/src/lib/uart8250.c trunk/

[coreboot] [commit] r6522 - in trunk/src/superio: nsc/pc87382 via/vt1211

Author: stepan Date: Wed Apr 20 03:03:58 2011 New Revision: 6522 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6522 Log: fix boards that still had some uart init remainders Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer Modified: trunk/src/superio/nsc/pc87382/superio.c

Re: [coreboot] Failed to launch windows 7 and two more questions ...

Hi Boris, Boris Shpoungin wrote: > We are considering to use coreboot for our developing board. Sounds good! > I downloaded latest version of coreboot + seabios and compiled it > for emulation. I tried to launch windows 7 in qemu with coreboot > bios (Note coreboot is not a BIOS. SeaBIOS is th

[coreboot] build service results for r6521

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6521 to the coreboot repository. This caused the following changes: Change Log: Drop baud rate init to an arbitrary baud rate from Super I/O code. See discussion at http://www.mail

[coreboot] Failed to launch windows 7 and two more questions ...

We are considering to use coreboot for our developing board. I downloaded latest version of coreboot + seabios and compiled it for emulation. I tried to launch windows 7 in qemu with coreboot bios and got the following error: "Windows failed to load because the firmware (BIOS) is not ACPI compa

[coreboot] coreboot hackaton in Prague

Hi all, I think it is time to remind the coreboot hackaton in Prague which will take place last weekend at the end of May (27,28,29) There is still a http://doodle.com/2n4h3gcugwvs6c9k poll if others wants to join in. The even will take place in Prague, Czech Republic. Most likely at the uni

[coreboot] [commit] r6520 - trunk/src/ec/lenovo/pmh7

Author: svens Date: Tue Apr 19 21:57:26 2011 New Revision: 6520 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6520 Log: Lenovo PMH7: add pmh7_touchpad_enable() Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle Modified: trunk/src/ec/lenovo/pmh7/pmh7.c trunk/src/ec/lenovo/p

[coreboot] [PATCH 3/4] pci1x2x: use pci_ops set_subsystem instead of custom code

Signed-off-by: Sven Schnelle --- src/southbridge/ti/pci1x2x/pci1x2x.c | 25 ++--- 1 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index 0628f1f..a3ec35c 100644 --- a/src/southbridge/

[coreboot] [PATCH] southbridge/ti/pci1x2x cleanup

Hi List, this patch series is a generic cleanup of the pci1x2x driver. Basically it does: - move register config from Kconfig to devicetree.cb - use the generic pci/cardbus functions - add proper subsystemid configuration - remove latency. cacheline size, bridge control register settings, as such

[coreboot] [PATCH 2/4] pci1x2x: add PCI1510 device IDs

Signed-off-by: Sven Schnelle --- src/include/device/pci_ids.h |1 + src/southbridge/ti/pci1x2x/pci1x2x.c |6 ++ 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6286cd6..03896c5 100644 --- a/src/in

[coreboot] [PATCH 1/4] pci1x2x: use devicetree register configuration

Signed-off-by: Sven Schnelle --- src/mainboard/nokia/ip530/Kconfig | 25 - src/mainboard/nokia/ip530/devicetree.cb |9 +++ src/southbridge/ti/pci1x2x/pci1x2x.c| 36 +- 3 files changed, 25 insertions(+), 45 deletions(-) diff --

[coreboot] [PATCH 4/4] pci1x2x: use cardbus_read_resources()/cardbus_enable_resources()

Signed-off-by: Sven Schnelle --- src/southbridge/ti/pci1x2x/pci1x2x.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index a3ec35c..bc4ee89 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c

Re: [coreboot] [PATCH] drop init_uart8250() calls from superio drivers

Am 15.04.2011 00:19, schrieb Stefan Reinauer: > See patch. Acked-by: Patrick Georgi -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] [commit] r6519 - in trunk/util/nvramtool: . cli

Author: jakllsch Date: Tue Apr 19 21:34:25 2011 New Revision: 6519 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6519 Log: Cast arguments to ctype(3) functions through (int)(unsigned char). Signed-Off-By: Jonathan Kollasch Acked-By: Jonathan Kollasch Modified: trunk/util/nvramto

[coreboot] [commit] r6518 - trunk/src/southbridge/intel/i82371eb

Author: oxygene Date: Tue Apr 19 21:21:27 2011 New Revision: 6518 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6518 Log: Fix compilation of all i82371eb boards when ACPI tables aren't generated Signed-off-by: Idwer Vollering Acked-by: Stefan Reinauer Modified: trunk/src/southbr

[coreboot] Dell Latitude D820

Hi All. Just joined the list to find out your opinion on whether or not I should put coreboot on my laptop. First off, what do I gain? I read it's faster but I don't really think my BIOS is slow. OR is it? Perhaps seeing is believing... Second, I've created a small txt file for reference. Felt t

Re: [coreboot] rtc wake up does not work on ASUS M2V-MX SE

Hi I think two things are missing: 1) Paste this into the dsdt table: Device(RTC0) { Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, Resou

Re: [coreboot] SuperI/O Access (Kernelspace)

On Fri, 2011-04-15 at 02:07 +0200, Peter Stuge wrote: > Jeremy Moles wrote: > > working great now .. via userspace > .. > > However, I'd like to be able to toggle the power on via a kernel > > driver as well, > > Why? > > > > but I'm having trouble accessing the same memory range from > > kernel

Re: [coreboot] potentially wrong uses of ifdef/if defined

On 04/19/2011 04:33 AM, Stefan Reinauer wrote: > ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT #ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif > ./src/northbridge/amd/amdk8/coherent_ht.c:#ifndef > CONFIG_MAX_PHYSICAL_CPUS_