[coreboot] Patch set updated: 367bfb7 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.

Keith Hui (buu...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/122 -gerrit commit 367bfb756f320019b0ea316a98dd260754cade4f Author: Keith Hui buu...@gmail.com Date: Wed Jul 27 23:06:16 2011 -0400 cpu/intel/slot_1: Init L2 cache on

[coreboot] git help: I can't get my whitespace cleanup in!

I'm trying to get this back in after we switched to git: http://review.coreboot.org/122 All seems good except some whitespace fixes. Making the fix is easy, submitting it through git is where I need help. Problem is I can't seem to get correct the sequence of commands. Right now I would... git

[coreboot] New patch to review: fa78e5d Do not compile nuvoton wpcm450 early init

Alexandru Gagniuc (mr.nuke...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/123 -gerrit commit fa78e5d1efc9b155537562ed385ad76ddc216a3c Author: Alexandru Gagniuc mr.nuke...@gmail.com Date: Mon Aug 1 03:54:58 2011 -0500 Do not compile

[coreboot] New patch to review: 3d487da Add PCI IDs vor VIA VX900 chipset

Alexandru Gagniuc (mr.nuke...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/124 -gerrit commit 3d487dab9ae1a16bb98d3077caa3ac5bc70f8a29 Author: Alexandru Gagniuc mr.nuke...@gmail.com Date: Mon Aug 1 05:16:20 2011 -0500 Add PCI IDs

[coreboot] Trac reminder: list of new ticket(s)

Ticket Owner Status Description #180 ste...@coresystems.de new ASRock E350M1 Gigabit Ethernet Problem #179 ste...@coresystems.de new Coreboot on GigaByte GA-8IEXP ver. 1.2 #178 ste...@coresystems.de new linux

Re: [coreboot] git help: I can't get my whitespace cleanup in!

Hi Keith, On Mon, Aug 1, 2011 at 12:41 AM, Keith Hui buu...@gmail.com wrote: I'm trying to get this back in after we switched to git: http://review.coreboot.org/122 All seems good except some whitespace fixes. Making the fix is easy, submitting it through git is where I need help. Problem

[coreboot] New patch to review: 523ae5d Use preferred style of fixed-width integer types

Jonathan A. Kollasch (jakll...@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/125 -gerrit commit 523ae5d776879621fabe6f338c1b8c808636a57d Author: Jonathan A. Kollasch jakll...@kollasch.net Date: Mon Aug 1 14:15:28 2011 -0500 Use

[coreboot] New patch to review: aad6f2a Add voltage control of southbridge and RAM on ms7135

Jonathan A. Kollasch (jakll...@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/126 -gerrit commit aad6f2ab566dffc055e7a1403348c3b38c120751 Author: Jonathan A. Kollasch jakll...@kollasch.net Date: Mon Aug 1 14:24:02 2011 -0500 Add

Re: [coreboot] libpci accesses in CAR, I need a suggestion

Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now chipset enable and probing for flash works in ramstage's top of hardwaremain function with this line included:

[coreboot] Patch set updated: 0f196d4 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.

Keith Hui (buu...@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/122 -gerrit commit 0f196d4cf39e680389a2098e10739d8545397203 Author: Keith Hui buu...@gmail.com Date: Wed Jul 27 23:06:16 2011 -0400 cpu/intel/slot_1: Init L2 cache on

[coreboot] New patch to review: df8d54c Initialize ACPI to prevent spurious events at OS boot

Jonathan A. Kollasch (jakll...@kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/127 -gerrit commit df8d54c4372f1e851c413c5903db20284eb57c06 Author: Jonathan A. Kollasch jakll...@kollasch.net Date: Mon Aug 1 15:17:08 2011 -0500

Re: [coreboot] libpci accesses in CAR, I need a suggestion

Tadas, On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkus devta...@gmail.com wrote: Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now chipset enable and probing for flash

Re: [coreboot] libpci accesses in CAR, I need a suggestion

On 8/1/11 1:28 PM, Marc Jones wrote: Tadas, On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkusdevta...@gmail.com wrote: Hi, thank you both for the answers. I have studied libpci from libpayload and removed that device list generation with mallocs. Done a bunch of trial-error cleanup and now