[coreboot] Patch set updated for coreboot: 2703285 libpayload: fix compile error with enabled USB_DEBUG

Mathias Krause (mathias.kra...@secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/653 -gerrit commit 270328581ec7881676f9d808483953026e473ff1 Author: Mathias Krause mathias.kra...@secunet.com Date: Fri Feb 17 12:23:26 2012 +0100

[coreboot] Trac reminder: list of new ticket(s)

Ticket Owner Status Description #186 ste...@coresystems.de new 3com 3c905tx / gpxe boot problem #185 ste...@coresystems.de new Vtech partial success #184 ste...@coresystems.de new Asus p2b with aty128 fails

Re: [coreboot] porting Coreboot to a new motherboard....

Hi Ron, I've been looking for DDR-SDRAM start-up tutorial. Is there any on the web outside of the JEDEC specs? Anyway, where are the codes located in the Coreboot source ? is it on the motherboard-specific codes? TIA, Darmawan On 2/15/12, ron minnich rminn...@gmail.com wrote: reading your

Re: [coreboot] porting Coreboot to a new motherboard....

Well, sorry about the noise. I forgot to mention that most of the RAM init I found was in the raminit.c of each of the northbridge. Is there any other important file(s) that I missed? Thanks, Darmawan On 2/20/12, Darmawan Salihun darmawan.sali...@gmail.com wrote: Hi Ron, I've been looking

Re: [coreboot] porting Coreboot to a new motherboard....

you commented out a number of calls to critical functions. You can't just simply set a register and assume it all works. Maybe I misunderstood. I think stepan's i945 code is a great example of how to turn on dram. Or you can look at sdram_enable in the lx440 code for the basic sdram startup

[coreboot] Patch merged into coreboot/master: 213eb80 Force SB800 bootblock to use I/O for PCI config

the following patch was just integrated into master: commit 213eb80a8a071403ca9448dc08b8e00b95f31e67 Author: Dave Frodin dave.fro...@se-eng.com Date: Thu Feb 2 14:56:23 2012 -0700 Force SB800 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the

[coreboot] Patch merged into coreboot/master: 3a72344 Force SB700 bootblock code to use I/O for PCI config cycles.

the following patch was just integrated into master: commit 3a7234421e81fa4a5b86be12de07c220ac0ccf5b Author: Dave Frodin dave.fro...@se-eng.com Date: Wed Feb 1 16:15:08 2012 -0700 Force SB700 bootblock code to use I/O for PCI config cycles. If PCI config cycles use MMIO instead of

[coreboot] Patch merged into coreboot/master: 0d7d667 Force SB600 bootblock to use I/O for PCI config

the following patch was just integrated into master: commit 0d7d6676e9c1def4d26432aa481752dbbabd3bec Author: Dave Frodin dave.fro...@se-eng.com Date: Thu Feb 2 14:50:02 2012 -0700 Force SB600 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the

[coreboot] Patch merged into coreboot/master: 2703285 libpayload: fix compile error with enabled USB_DEBUG

the following patch was just integrated into master: commit 270328581ec7881676f9d808483953026e473ff1 Author: Mathias Krause mathias.kra...@secunet.com Date: Fri Feb 17 12:23:26 2012 +0100 libpayload: fix compile error with enabled USB_DEBUG Commit c4348d0 (libpayload: Remove

Re: [coreboot] porting Coreboot to a new motherboard....

Thanks Ron. I'm looking into it. On 2/20/12, ron minnich rminn...@gmail.com wrote: you commented out a number of calls to critical functions. You can't just simply set a register and assume it all works. Maybe I misunderstood. I think stepan's i945 code is a great example of how to turn on